CIMdata PLM Industry Summary Online Archive
2 July 2012
Implementation Investments
Cadence Digital PHY Design IP Adopted by Brite Semiconductor
Cadence Design Systems, Inc. today announced that its collaboration with Brite Semiconductor has enabled the integration of the Cadence® DDR Soft DLL PHY intellectual property (IP) into the design ecosystem for manufactured devices from Semiconductor Manufacturing International Corporation (SMIC). Specifically, Brite and Cadence plan to integrate the DDR PHY IP with I/Os for implementation on SMIC 130nm, 65nm, 55nm, and 40nm process technologies. Brite Semiconductor plans to tapeout a test-chip platform, with the memory subsystem IP, providing valuable insight into this ultra low-power, high-performance solution which is ideal for mobile devices such as smartphones, tablets, and other consumer electronic products.
"The collaboration between Cadence and Brite places market-leading memory IP in the SMIC ecosystem providing SoC designers with easy access to this low-power, high-performance, technology," said Martin Lund, senior vice president of Research and Development, SoC Realization Group at Cadence. "We look forward to a close and on-going relationship with Brite to continue developing leading-edge memory solutions driving higher levels of performance and functionality in today's mobile devices."
"We are pleased to extend our partnership with Cadence to deliver the superior wide range DDR PHY solution of our ASIC products," said Dr. Charlie Zhi, Chief Executive Officer at Brite Semiconductor. "To successfully deliver customized SoCs, we must have an area efficient, configuration flexible, and multi-standard support including DDR2, DDR3, LPDDR1, LPDDR2, memory PHY solution in current and advanced SMIC process technology nodes. This partnership is affording Brite the opportunity to seamlessly integrate DDR PHY, and corresponding features, into ASIC products and providing our customers a significantly competitive advantage. Furthermore, this collaboration would create the opportunity for rapid time to market execution, and reduce the entry barrier for designing in advanced process nodes."
Cadence Memory IP Solutions
Cadence has over 400 design wins for its DDR controllers and PHYs. All memory IP from Cadence is programmable to interface with multiple memory technologies. Low-power modes, small area, and high performance are possible through full digital DLL implementation. A built in loopback feature provides at-speed testability for full-silicon characterization without the need for expensive ATE. Cadence DDR controllers, and DDR PHYs support the new DFI 3.1 specification for seamless connectivity to DDR controllers.
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