CIMdata PLM Industry Summary Online Archive

30 August 2004

Product News

Mentor Graphics and Denali Collaborate to Deliver High-Quality Intellectual Property for PCI Express and Advanced Switching Interfaces

Denali Software Inc. and Mentor Graphics Corporation announced a collaborative effort to ensure high quality and ease of deployment for the Mentor Graphics® PCI Express intellectual property (IP) cores. Mentor Graphics will use Denali's PureSpec verification IP product to confirm its PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect (ASI) interface standards, and interoperable with other system designs. Through this effort, Mentor will provide its customers with the highest possible quality IP, while lowering the cost of deployment and integration.

"Denali is a leader in verification solutions for PCI Express and Advanced Switching designs and we are pleased to collaborate with them on this effort," said Michael Kaskowitz, general manager, Intellectual Property Division, Mentor Graphics. "Compliance and interoperability are key requirements for success and this collaboration will move us a long way towards this goal. Working with Denali, we are able to increase the quality and efficiency of our PCI Express and ASI capable IP solutions, while strengthening the Denali solution by sharing our knowledge and experience as a leading IP provider."

About Mentor Graphics PCI Express IP

•  Scalable architecture:   x1, x2, x4, x8, x12, x16 lanes at 2.5Gbps
•  Supports PCI Express endpoint, bridge, switch and root complex applications
•  Low latency implementation
•  Power management, AER, hot plug, multiple links per port
•  Up to 4,096 byte packets for Tx & Rx and retry buffers
•  64 or 128 bit FIFO based back-end interface
•  8 or 16 bit PIPE interface to SerDes PHY
•  Full support for ASI in the Data Link Layer, which may be used independently of the Transaction Layer.

All Mentor Graphics IP cores are delivered to the highest quality standards. The PCI Express Configurable Port will be available in VHDL and Verilog source code, with testbench and documentation. For more information on Mentor Graphics IP cores, please visit:

PureSpec is a widely used verification IP product for simulating and verifying PCI Express and Advanced Switching Interconnect designs. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint and PCI Express to PCI bridge. Within PureSpec, all protocol layers-physical, data link and transaction-of the PCI Express/ASI specification are modeled and can be simulated concurrently or independently. PureSpec contains thousands of assertions which are monitored during simulation to ensure compliance with the specification and interoperability with other system devices. PureSpec provides seamless integrations to EDA tools and verification language, and is available for customer evaluation at:


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