CIMdata PLM Industry Summary Online Archive

22 October 2007

Product News

Virage Logic Expands Silicon Aware Intellectual Property (IP) Offering with New 65-Nanometer Memory and Logic Products

Virage Logic Corporation announced the availability of a broad new family of 65-nanometer (nm) products -- SiWare Memory compilers and SiWare Logic libraries. This new offering, based on more than two years of early 65nm silicon successes, broadens the company's Silicon Aware IP portfolio and enables semiconductor companies to design faster, lower power and more area efficient System-on-Chips (SoCs) while achieving higher yields.

The SiWare Memory product line provides a dashboard that enables SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. This "dashboard control" capability is critical at 65nm where design and process complexities require sophisticated management of the various tradeoffs in order to effectively meet stringent end-product requirements and increasingly narrow market windows. (Virage Logic also today announced new Silicon Aware memory test and yield analysis products. See related press release titled, "Virage Logic Broadens its Silicon Aware IP Offering with New Release of the START Memory System.")

In addition to being optimized for design-for-manufacturing (DFM), the SiWare Logic product line offers SoC designers the ability to manage tradeoffs between area, speed and power. The SiWare Logic library architectures -- high-speed, high-density and ultra-high-density -- can also be extended with ultra-low-power (ULP) kits for power management and engineering change order (ECO) kits for metal-only design modifications.

"Since the first introduction of our 65nm offering with TSMC, UMC and Freescale in 2004, we have leveraged our early experience to provide designers with an advanced product offering that addresses tough 65nm challenges," said Brani Buric, vice president of product marketing and strategic foundry relationships at Virage Logic. "Our SiWare Memory and SiWare Logic offerings incorporate what we've learned to provide a rich set of performance-enhancing, area-saving, power-optimizing and yield-accelerating options for SoC designers to control as they develop competitive products."

"Our successful, long-standing relationship with Virage Logic spans various process technologies for multiple foundries, and enables us to utilize their portfolio of highly differentiated IP solutions in our industry-leading multi-mode VDSL2 and gateway products," said Shekhar Khandekar, vice president of operations at Ikanos. "As a result, our products are able to power the processing and distribution of triple play services in the carrier infrastructure and at the customer premise."

"Virage Logic was one of the pioneers in establishing the third-party commercial IP market more than 10 years ago and they have a long track record of being first to deliver quality, silicon proven products on each new node," said Rich Wawrzyniak, senior analyst at SEMICO Research Corporation. "I am impressed with the breadth of their new 65nm SiWare Memory and SiWare Logic offering and the attention to detail in terms of providing a complete capability set. With the ability to manage and optimize speed, power, area and yield tradeoffs, the SiWare product family enables designers to successfully address the challenges of 65nm design."

Availability and Pricing

SiWare Logic libraries and SiWare Memory compilers, including single port and dual port SRAMs and register files, are available now for TSMC's 65nm GP and LP processes. Project pricing starts at $70,000. SiWare IP supports all major electronic design automation (EDA) tool flows such as those offered by Cadence, Magma and Synopsys.

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