CIMdata PLM Industry Summary Online Archive

24 October 2007

Implementation Investments

Elektrobit Corporation Selects Catapult C Synthesis to Design Next-Generation Wireless Hardware

Mentor Graphics Corporation announced that Elektrobit Corporation ( EB ), a company delivering cutting-edge embedded technology solutions to automotive and wireless markets has selected the Catapult® C Synthesis product to accelerate creation of its next-generation wireless technology. EB selected the Catapult C Synthesis product based on the tool's ability to synthesize pure ANSI C++ and increase hardware designer productivity up to 10x.

EB is using the Catapult C Synthesis product to design advanced next-generation wireless hardware, including ultra-high-performance hardware that enables next generation mobile WiMAX. When implementing complex designs like a multiple input/multiple output (MIMO) algorithm, hardware designers must make many micro-architecture decisions that can have a large impact on performance, area or power consumption in the final implementation. The Catapult C Synthesis product enables automatic RTL creation from an ANSI C++ source, allowing users to quickly implement their designs, evaluate how their decisions impact the design, and make adjustments with minimal effort.

"Catapult delivers a level of productivity that we are unable to achieve using hand-coded RTL methodologies. The productivity benefits come from automatic RTL creation that eases design exploration, plus verification efficiencies delivered by the C testbench Catapult's error-free RTL code," Ari Hulkkonen, Director, Wireless Systems, EB. "As we move to implement more complex designs with Catapult, we routinely observe 5x productivity improvements over manual RTL, as well as efficient performance and area values depending on the application. This is a very valuable tool for anyone designing wireless hardware."

The Catapult C Synthesis tool is the first product to automatically generate RTL from a pure ANSI C++ source where both the core algorithm and interface are untimed. This productivity improvement gives designers time and freedom to automatically perform detailed design exploration of different micro-architectural options and interface scenarios to quickly achieve fully optimized hardware designs for either ASIC or FPGA implementations. Catapult's SystemC verification extension offers integration to industry standard SystemC verification platforms and tools providing a complete ESL design and verification methodology.

"Companies like EB are designing the backbone of our future communications infrastructure. We are pleased that EB has chosen Catapult C Synthesis to help create their advanced products," said Simon Bloch, general manager of Mentor Graphics' Design Creation and Synthesis Division. "Through extensive pilot projects and now production usage at EB, Catapult has been proven to produce high-quality RTL designs far faster than hand-coded methods."

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