CIMdata PLM Industry Summary Online Archive

8 October 2008

Product News

Cadence Custom Lithography Technology Addresses 22-Nanometer Semiconductor Manufacturing

Cadence Design Systems, Inc. announced the availability of software that optimizes custom lithographic source illumination, a new capability in its integrated source mask optimization (SMO) technology family for IC manufacturing at 22 nanometers and beyond. Optimized custom litho source illumination delivers the superior process window and improved two-dimensional image fidelity required for 22-nanometer semiconductor manufacturing.

Cadence® collaborated with Tessera Technologies, Inc. to incorporate the custom source illumination manufacturing awareness into its SMO software technology family. The new capability is integrated into the Cadence resolution enhancement technology (RET) flow for both single- and double-patterning lithography, and it delivers exceptional ease of use and automation to accelerate both technology development and production ramps.

“The flexibility to take full advantage of diffractive optical elements is essential to achieving high yields at the 22nm node,” said Michael Bereziuk, executive vice president of Imaging & Optics at Tessera. “Tessera is pleased to work with Cadence to provide solutions to the SMO challenge that utilize our full design expertise and ten years of experience with off-axis illumination.”

The collaboration between Cadence and Tessera focuses on Tessera’s DigitalOptics™ technologies, which enable one of the broadest range of control available today, providing conventional, gray-tone, and free-form litho source illumination. Effective source mask optimization requires that the full degrees of freedom and actual constraints of the illumination design are incorporated into the design algorithms. Incorporating these more advanced models into the Cadence SMO software provides powerful new capabilities to the entire user community.

At 22 nanometers and below, conventional computational lithography techniques such as model-based OPC and the existing range of RETs are not sufficient to deliver the required silicon pattern fidelity. The Cadence source mask optimization technology enables more accurate computational lithography assessments and tradeoffs that improve pattern fidelity and enable increased product yield. This is accomplished by taking into account the RET/OPC recipes and models, mask manufacturability rules, polarization pattern in the lens pupil, Jones matrix of the projection lens, optical parameters of the resist stack, resist diffusion, and other key factors.

A key differentiation of the Cadence technology is its ability to optimize the litho source illumination based on the printability of two-dimensional layout structures through a process window, rather than just through critical dimension (CD) requirements of the design. The Cadence source mask optimization solution is also applicable to both conventional and free-form illumination patterns.

“We're going beyond traditional DFM to a co-optimized design and manufacturing approach with this collaboration,” said Dr. Dipu Pramanik, vice president of silicon signoff and optimization at Cadence. “This collaboration with Tessera will help our customers quickly achieve their computational lithography implementation and technology entitlement goals thereby reducing their overall cost of ownership.”

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