CIMdata PLM Industry Summary Online Archive
17 May 2004
Product News
Sierra Design Automation Unveils Breakthrough Unified Physical Synthesis And Prototyping Solution For Multi-Million Gate Designs at 90 Nanometer And Below
Sierra Design Automation, Inc. ( http://www.sierra-da.com ), an IC implementation startup founded in January of 2003, announced the production availability of PinnacleT, its next-generation IC implementation solution for multi-million gate nanometer design.
Pinnacle, Sierra's flagship product, is the industry's first IC implementation solution developed specifically to meet the high capacity, short turn around time and quality of results (QoR) demands of large designs targeted at manufacturing processes of 90 nanometer and below. Its physical synthesis technology and breakthrough product architecture speeds design closure by 5x to 10x over last-generation tools, slashing turnaround time from days to hours, and eliminating a major recognized bottleneck in the physical design of multi-million gate nanometer chips. Pinnacle's open architecture and ultra-compact database can handle 10 Million gates flat-chips or blocks-on a 32-bit machine. Pinnacle scales to 50+ Million gate hierarchical designs on a 64-bit machine and integrates into customer's existing design flows.
In current generation implementation tools, physical synthesis is the biggest capacity bottleneck in the IC implementation flow. Existing physical synthesis approaches rely extensively on computationally expensive techniques, such as iterative improvement and brute-force trial-based optimization resulting in unacceptably long turnaround time. In addition, traditional physical prototyping approaches are inaccurate since their product architectures are decoupled from the final implementation systems. This results in mis-correlated timing analysis, congestion analysis and an inability to predict the final performance after implementation.
Sierra has developed a patent-pending, physical synthesis approach that can optimize 10 Million gates flat in an overnight runtime. Pinnacle's shorter turnaround time is attributed to new technological advances in the area of performance bottleneck detection and analytical optimization technology. This new approach to physical synthesis is helping Sierra's customers achieve design closure on multi-million gate designs in a fraction of the time it takes them with their existing design flows.
"Fujitsu is continually addressing our customer needs by upgrading our IC implementation flows to achieve rapid closure on large designs efficiently, and to satisfy the design requirements of 90 nanometer processes and emerging smaller geometries," said Noboru Yokota, Director, Advanced Technology Development Group of Fujitsu Microelectronics America, Inc. "Sierra's Pinnacle physical design system has demonstrated the capacity, speed and implementation quality needed for our ASIC evaluation designs. Fujitsu is incorporating Pinnacle's physical design system into our IC implementation flow. Additionally, we are analyzing Pinnacle's flexible product architecture for use with AccelArrayT, Fujitsu's new ASIC design platform, and expect it will enable us to offer a very high-capacity, fast turn-around-time design flow for our AccelArray customers."
Pinnacle's ultra-compact database has the industry's highest capacity and the smallest memory footprint. This enables both prototyping and implementation to be performed in the same unified environment. Implementation engines are directly used during prototyping, resulting in very high correlation between the two steps. Pinnacle also addresses the complex challenge of constraint validation for "dirty" design data using its proprietary physical synthesis technology that is robust in the presence of ill-formed constraints. In addition, for nanometer design variability-such as operational, process and in-die-Pinnacle enables designers to simultaneously analyze and optimize multiple design corners and modes, eliminating weeks or months of iteration around different variability scenarios.
"Our customers are designing multi-million gate SoCs with aggressive time-to-market requirements. In order to meet our customer's challenging design requirements, we are continuously seeking high capacity and productive chip implementation methodologies," said Hideki Yamada, EDA Chief Technologist, ASIC and Foundry BU, Toshiba America Electronic Components, Inc. "We found that the run time of Sierra's Pinnacle system was under 12 hours for placement and optimization on our complex 6 million gate design, utilizing a flat physical design flow on a 32-bit Linux machine. As a result, with Sierra's Pinnacle, we are able to run the implementation process multiple times in the customer's limited timeframe to deliver the optimized result. We are interested in integrating Sierra's Pinnacle into our existing flows for our SoC design productivity improvement."
Pinnacle has a rich set of features and it integrates in customer's existing flows. It has built-in global and trial routing technology and has demonstrated excellent correlation with leading detailed routing tools at multiple customers. Pinnacle's built-in static timing analysis engine has demonstrated very good correlation with sign-off timing analysis tools and its delay calculation technology has also been correlated closely with SPICE.
Sierra Pinnacle is available now with prices beginning at $395,000 U.S. for a one year license.
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