CIMdata PLM Industry Summary Online Archive
13 May 2004
Product News
Zenasis Introduces Breakthrough in ASIC Timing Optimization; ZenTime Quickly Eliminates Large Timing Problems
Zenasis Technologies, Inc. ( http://www.zenasis.com ) announced ZenTimeT, the first product to use its unique hybrid optimization technology. The new tool helps ASIC and SOC design teams to reach their target performance by injecting large timing gains into their designs in just the right places. Using a hybrid of transistor, logic, and physical optimization, ZenTime can generate timing gains that are 2-4x larger than conventional timing closure tools. In today's 130-nanometer process, ZenTime can gain over 50 MHz in additional performance, making it the only tool capable of closing the large timing shortfalls that are common in nanometer-era designs.
As semiconductor feature sizes drop, design teams are finding it increasingly difficult to reach their timing targets with certainty. Timing closure tools that simply re-buffer and re-size the critical paths can only affect timing by small amounts. Physical synthesis greatly improves timing accuracy but only has a limited ability to improve the actual timing. Global floorplanning helps minimize long-wires but it's a tricky, manual, non-deterministic process to try to use floorplan adjustments to improve timing.
ZenTime uses a new hybrid-optimization technology to obtain a fundamental boost in design timing. By operating simultaneously at the transistor, gate, and physical levels, hybrid optimization combines the benefits of custom-cell crafting, physical optimization, and placement accurate timing. ZenTime uses placement accurate timing to identify timing road-blocks, transistor-level optimization to break the road-blocks by crafting context-specific cells for the critical logic, and physical optimization to restructure surrounding logic and capitalize on the local improvements. By optimizing at the transistor-level ZenTime often finds ways to improve timing using fewer or smaller transistors and fewer inter-cell wires. As a result, ZenTime improves timing without introducing power, area, or signal-integrity penalties. In addition, no change is required to existing synthesis or physical design tools when ZenTime is added to a flow. The crafted cells inserted by ZenTime use the same cell layout architecture as the standard cell library, so place-and-route tools see no difference between the standard cells and the new crafted cells.
"We're a ZenTime beta site," said Jay McDougal, IP Design Methodology Program Manager at Agilent Technologies. "From our evaluation thus far, we've found it to be a unique EDA tool that can help us improve performance on some of our most critical designs. With ZenTime we've seen significant timing improvement on one of our most challenging processor cores, and that was after applying our best physical synthesis techniques."
"At Renesas we're looking both at how ZenTime can improve the performance of our micro-controllers, and help our ASIC customers reach aggressive timing targets," offers Yoshio Inoue, Manager of the EDA Methodology Group at Renesas Technology Corp. a joint venture between Hitachi, Ltd. (TSE:6501) (NYSE:HIT) and Mitsubishi Electric Corporation (TSE:6503). We've used an early version of ZenTime to close timing shortfalls of 15-20%. I've seen no other tool capable of generating that much timing closure on high performance designs."
ZenTime is currently in early deployment at a limited number of beta sites. The product will be released for customer shipments this month and will be available as a term-based license for $195,000 per year.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.