CIMdata PLM Industry Summary Online Archive

24 May 2004

Product News

Cadence Delivers 90-Nanometer Reference Flow to Optimize Nanometer Design for IBM-Chartered Process Platform

Cadence Design Systems, Inc. announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow integrates intellectual property (IP) developed by Artisan Components, Inc. for the IBM-Chartered cross-foundry design enablement program. Developed in conjunction with IBM, this RTL-to-GDSII reference flow-based on the Cadence® EncounterT digital IC design platform-is optimized across the front-to-back design chain. It offers chip designers a predictable path for system-on-chip (SoC) design from RTL to first-pass silicon.

The reference flow incorporates Cadence technologies including Encounter RTL CompilerT global synthesis, Encounter TestT solutions, and NanoRouteT unified routing and physical optimization.

The joint reference flow uses a wire-centric methodology to address key 90-nanometer SoC issues, including low power design, signal integrity, and design-for-test to provide the highest quality of silicon (QoS). QoS measures a design's physical characteristics using wires in terms of improved area utilization, higher performance and lower power consumption.

"The combination of advanced process technology, jointly developed by IBM, Chartered and leading-edge Cadence technologies, allows customers to benefit from improved quality of silicon resulting in reduced area, lower power and better performance," said Lavi Lev, executive vice president and general manager, IC Solutions, Cadence. "Ultimately, our goal is to provide mutual customers with a predictable path to first silicon."

"The Cadence Encounter platform focuses on some of the more challenging issues with regard to 90-nanometer design, and we're pleased to be collaborating with Cadence as a means for customers to accelerate their path to silicon," said Kevin Meyer, vice president of worldwide marketing and services at Chartered. "By leveraging the IBM-Chartered design enablement program, customers enjoy additional benefits such as design portability and a flexible sourcing model."

To access the 90nm reference flow kit, send an email to IBM_Foundry_Support@cadence.com This reference flow kit contains a reference design, documentation and scripts to run the reference flow. Additional information on the reference flow can be found in the product brief at http://www-306.ibm.com/chips/techlib/techlib.nsf/productfamilies/Foundry (Due to the length of this URL, it may be necessary to copy and paste this hyperlink into your Internet browser's URL address field. You may also need to remove an extra space in the URL if one exists.)

On Wednesday, June 30, 2004, Cadence, Chartered and IBM will hold a free webinar on how to enhance design team productivity and silicon reliability with the Cadence Reference Flow for the IBM-Chartered 90-nanometer CMOS process. To register or obtain additional information on this webinar, visit http://webevents.broadcast.com/ibm/foundry/062304/index.asp  

 

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