CIMdata PLM Industry Summary Online Archive
24 May 2004
Product News
Blue Pearl Software to Automate the Process of RTL Closure for IC and Electronic System Design
Blue Pearl Software, Inc. ( http://www.bluepearlsoftware.com ), an electronic design automation (EDA) company, was launched to automate the process of RTL Closure for integrated circuit (IC) and electronic system design. Blue Pearl's software will enable functional design, timing and design-for-test (DFT) closure at the register transfer level (RTL). Its analysis and verification software identifies functional issues in the RTL design, and reduces the number of design iterations required to meet timing and test requirements by resolving critical timing path and DFT issues. Blue Pearl's proprietary technology helps to reduce both time-to-market and design costs, and reduces or eliminates the substantial costs of functional design errors.
Blue Pearl's management team, directors, and advisors have extensive experience in developing successful EDA companies. Smith formerly led Exemplar Logic Inc., TransEDA PLC, and Crosscheck Technology Inc. Prab Varma, Blue Pearl's vice president of engineering and CTO, was formerly president of Veritable Inc. and was vice president of engineering at Duet Technologies and Crosscheck Technology. Other executives at the company include CFO Rick Dissly, former CFO of Photon Dynamics, Inc.; and vice president of worldwide sales, Carol Hallett, who has held executive sales positions with TransEDA, CAD Design Software, and RoyoCAD Inc. Athanasios "AK" Kalekos, formerly a general partner with Telos Ventures and senior vice president with Cadence Design Systems, has joined Blue Pearl's Board of Directors. The company's technical advisors include Michael Bohm, vice president of engineering and CTO of AccelChip; and Mark Fuccio, CEO of Tactics, Inc., who has held management positions with Philips Labs, Trilogy Systems, Daisy Systems, and SGI.
Blue Pearl provides ASIC, structured ASIC and FPGA designers with functional design closure by checking complex RTL design and verification issues such as synchronization of data crossing clock domains, initialization, and FSM behavior verification. The technology accelerates timing closure by identifying false paths and automatically generating timing constraints, and provides early DFT closure by identifying testability problems before synthesis. Blue Pearl's first products will be available in the third quarter of 2004.
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