CIMdata PLM Industry Summary Online Archive
17 May 2004
Product News
Silicon Design Systems Announces Convergent Routing Solution Aimed at Nanometer IC Designs
Silicon Design Systems, Inc. announced K-RouteT, which it believes is the industry's first truly concurrent routing technology to solve IC design closure issues magnified by submicron and nanometer technology. Its adaptive, fine-grained routing architecture (AFRA) simultaneously uses routing, extraction, analysis and optimization engines to complete tightly constrained designs faster and more predictably. The convergent router automatically recognizes and fixes all potential geometrical, timing and signal integrity violations, allowing for smaller design area and significantly improved performance, power consumption and time to tape-out.
Silicon Design System architecture allows several engines to work together, solving each problem simultaneously from various domains - geometrical, timing, noise and signal integrity. Adaptive algorithms enable designers to make intelligent choices, given constraints, to achieve convergence.
The Silicon Design Systems approach addresses a recognized industry need. According to Dr. Naveed Sherwani, President and CEO of Open-Silicon: "Despite evolutionary enhancements, schedule predictability of high-end designs remains an elusive goal because of the numerous iterations required. To truly solve the problem requires a fresh approach such as that offered by Silicon Design Systems."
Ram Ofir, Vice President Engineering at Zoran Corporation said, "Having worked closely with Silicon Design Systems' unique technology, we were able to achieve significant area reduction. The SDS solution offered predictability, and we were able to make last-minute functional changes just prior to tape-out. We are pleased to start working with K-Route because we consider this technology to be a very promising approach for physical design closure."
Bob Divivier, Vice President Engineering at Zettacom said, "Silicon Design Systems is tackling the design challenges of complex nanometer-scale ICs head on, solving issues, rather than minimizing them, with its Physical Design Closure system. Analyzing and addressing layout effects while routing, and not afterwards, is the optimal way to achieve a clean design ready for tape-out."
The traditional physical design convergence flow includes placement and routing, followed by design analysis and manual or semi-manual repairs. Despite the use of advanced point tools, nanometer design teams continue to struggle with issues such as timing, signal integrity and design for manufacturability. Solving one violation in one domain likely generates new violations elsewhere, creating an endless-loop scenario in which it is nearly impossible to predict convergence. Taking a novel, integrated concurrent approach, K-Route extracts and analyzes timing and signal integrity at a much finer level of granularity than other tools, simultaneously optimizing all the domains. It recognizes and fixes potential violations, resulting in true closure and violation-free, optimal design. This new adaptive routing architecture is key to addressing upcoming Design for Manufacturability (DFM) challenges that take center stage at sub-130nm technology nodes.
"Silicon Design Systems had used commercial backend tools for the last seven years; we knew first-hand the frustration of closure predictability problems as we searched in vain for commercially available EDA tools to address them," said Naeem Zafar, president and CEO of Silicon Design Systems: "Deciding to tackle the issue ourselves, we developed K-Route as a novel 'think-then-route' approach, rather than the traditional 'route-then-think' technique. Unlike methodologies that merely minimize violations, K-Route actually solves them, letting companies achieve detailed closure, instead of statistical closure, and create far more efficient design than with traditional cell-based ASIC flows."
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