CIMdata PLM Industry Summary Online Archive
24 May 2004
Product News
Synopsys Announces Galaxy and Discovery Platform Support for 90 Nanometer IBM-Chartered Process
Synopsys, Inc. announced validation of the GalaxyT Design and DiscoveryT Verification platforms with the 90 nanometer (nm) process platform common to both IBM and Chartered Semiconductor Manufacturing. Using Artisan Components' 90nm SAGE- XT standard cell libraries, Synopsys has verified the complete design process from RTL through GDSII verification, demonstrating the ability of the Galaxy and Discovery platforms to address the full range of 90nm design challenges. Synopsys Professional Services performed the validation of the Galaxy and Discovery platform tools with the Artisan libraries as part of the IBM-Chartered cross-foundry design enablement program.
The Galaxy Design Platform allows semiconductor designers to implement complex high-performance 90nm designs into a single GDSII representation that could be manufactured at either IBM or Chartered. The combination of design and verification platforms, multiple libraries, and multiple-source manufacturing provides circuit designers a unique combination of design capability, flexibility, and worldwide support.
"Building on the 130 nanometer reference flows we developed, Synopsys has worked with IBM, Chartered and Artisan to create a new flow addressing the challenges of 90 nanometer design. The fact that Synopsys Professional Services could exercise the entire flow using a standard cell block in only two days is testament to the effectiveness of the Galaxy and Discovery platforms and the maturity of the Synopsys flow," said Glenn Dukes, vice president of Synopsys Professional Services. "The ability to quickly transform RTL into a fully validated GDSII is key, but coupling this with the ability to take this GDSII to multiple foundries creates significant new strategic options for designers."
The Synopsys ( http://www.synopsys.com ) solution spans implementation, verification and IP, providing a complete integrated approach to the design of complex high performance 90nm digital devices. The Galaxy Design Platform links Design Compiler® logic synthesis, JupiterXTT design planning, Physical Compiler® physical implementation, AstroT signal integrity and design-for-manufacturing (DFM) aware detailed placement and routing, and PrimeTime® sign-off timing analysis through the MilkywayT database, increasing accuracy and consistency throughout the design process and reducing the number of design iterations. The Artisan libraries provide three voltage threshold (Vt) levels, allowing Power CompilerT to simultaneously optimize performance, area, switching and leakage power with the optimal mix of cells and Vt levels. The 1-pass test synthesis and comprehensive DFT rule checks are supported through DFT CompilerT, while manufacturing test pattern generation supporting both stuck-at and delay faults and failure diagnosis is supported by TetraMAX®. Final design sign-off is supported by PrimeTime SI, Star- RCXTT, and HerculesT using technology files available from IBM or Chartered. The Discovery Verification Platform provides multi-language functional verification through VCS® and Formality® for equivalence checking. HSPICE® is also supported using models available from IBM or Chartered. A broad range of DesignWare® implementation and verification IP is also supported for further productivity gains.
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