CIMdata PLM Industry Summary Online Archive

27 May 2004

Company News

AccelChip, ChipX Announce Partnership to Automate IC Design Flows

AccelChip Inc. ( http://www.accelchip.com ) announced it is extending its AccelChip Silicon vendor Alliance Program (ASAP) through a partnership with ChipX ( http://www.chipx.com ), a manufacturer of Structured ASICs. Under terms of the agreement, AccelChip will enhance its AccelChip® DSP Synthesis tool to provide highly optimized results for ChipX's Structured ASIC products. When combined with AccelChip's AccelWare® DSP parametric libraries and industry-standard IC flow, designers targeting ChipX devices will now have a highly optimized, top-down, language-based flow for DSP design.

Over the past several years, the escalating cost of full custom, cell-based ASICs and the inherent performance limitations of FPGAs have driven designers to seek high performing, but more cost-effective alternatives. Designed to reduce the high NRE (non-recurring engineering) costs traditionally associated with cell-based approaches, Structured ASICs feature pre-configured patterns of logic cells, memory, and I/O. This architecture allows engineers to customize their logic during the application of the final few metal layers of the device, and, in the process, reduce NRE cost and shorten the development cycle.

AccelChip provides software and services that automate the path from DSP algorithms to silicon, accelerating the DSP design cycle and increasing the quality of results. Unlike other flows that require manual translation of MATLAB to proprietary C languages, graphical capture tools, or RTL (register-transfer-level), AccelChip products automate this flow while providing design exploration and a complete verification environment.

By extending this flow with device-specific optimizations, ASAP levels the playing field for all semiconductor vendors who cannot afford to invest millions in their own proprietary flow. The program achieves this goal by supporting industry-standard IC design flows based on RTL design methodology and by developing resource description models for program participants. Besides ChipX, current program participants include Altera, Elixent, and Xilinx.

AccelChip will demonstrate its DSP Synthesis tool featuring the ChipX Structured ASIC flow at the 41st Annual Design Automation Conference (DAC) in San Diego, California (June 7-11, 2004), booth 1539. A new version of AccelChip DSP Synthesis with support for ChipX's Structured ASIC products will be available in June 2004.

 

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