CIMdata PLM Industry Summary Online Archive

27 May 2004

Company News

Static Timing Analysis to be Demonstrated by Hier Design at 41st Design Automation Conference

Hier Design Inc. will demonstrate its new TimeAheadT static timing analysis environment at the 41st Design Automation Conference (DAC) in Booth Number 4343 from Monday, June 7, through Thursday, June 10, at the San Diego Convention Center in San Diego, Calif. Its PlanAheadT hierarchical floorplanner, the core of its silicon virtual prototyping solution for high-end field programmable gate arrays (FPGAs), will also be demonstrated continuously during DAC.

The TimeAheadT static timing analysis environment helps FPGA designers find and fix design performance problems earlier, before place and route. It offers fast feedback on potential timing bottlenecks, enabling designers to create effective floorplans prior to running place and route, as well as make floorplan adjustments after it is completed. A complete timing analysis environment, it is tightly integrated with the PlanAhead hierarchical floorplanner. The combination of TimeAhead and PlanAhead shortens the design cycle by providing a faster, less iterative path from logic synthesis through physical design while increasing design performance.

To schedule a private demonstration of either PlanAhead or TimeAhead, visit: http://www.hierdesign.com . Or, contact Dino Caporossi, vice president of marketing at Hier Design. He can be reached at (408) 982-8257 or via email at dino@hierdesign.com

 

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