CIMdata PLM Industry Summary Online Archive
26 May 2004
Implementation Investments
Renesas Technology Adopts Synopsys' Jupiter XT Design Planning Flow for 90 Nanometer Designs
Synopsys, Inc. ( http://www.synopsys.com ) announced that Renesas Technology Corp., a joint venture between Hitachi, Ltd. and Mitsubishi Electric Corporation has adopted Synopsys' JupiterXTT design planning flow to improve turnaround time on chips for leading consumer electronics devices. Renesas Technology is expanding its commitment to Synopsys' GalaxyT Design Platform through this adoption as it already uses Synopsys' Design Compiler®, PrimeTime®, Star-RCXTT and AstroT products.
Renesas Technology adopted Synopsys' JupiterXT design planner because it enables Renesas Technology designers to save valuable time by creating high quality floorplans in significantly fewer iterations. JupiterXT provides Renesas Technology with a convergent design flow due to high correlation of placement, timing, extraction and power network analysis engines between JupiterXT and the rest of Galaxy's implementation and sign-off tools. JupiterXT's automatic embedded macro placement, power network analysis and power network synthesis will also help Renesas Technology eliminate the "ping-pong" effect that normally occurs between chip-level and block-level floorplanning.
"We needed a 90 nanometer solution for design planning and, after evaluating Synopsys' JupiterXT, found that it produced results comparable to those created by tedious manual design iterations, performance necessary for our designs, which feature very high gate counts and multiple embedded macros," said Hisaharu Miwa, Department Manager of EDA Technology Development Department at Renesas Technology. "The decision to use JupiterXT solidifies a long-term commitment to Synopsys technology and recognizes JupiterXT's ability to produce the fastest path to high-quality results."
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