CIMdata PLM Industry Summary Online Archive
24 May 2004
Product News
Apache Enhances RedHawk-SDL for Low-Power Designs and Addresses Timing Impact Issues Facing Nanometer Designs
Apache Design Solutions announced new capabilities in its flagship product, RedHawk-SDL, to address dynamic power integrity issues for advanced low power designs. The new capabilities also address the critical need to accurately analyze the impact of dynamic supply noise to chip timing.
RedHawk-SDL is a full-chip cell-based Vectorless Dynamic physical power integrity solution with integrated transistor-level characterization for assured accuracy. The latest enhancements enable design teams to verify the impact of dynamic power supply noise on chips that employ low power design techniques and timing of high performance SoCs.
Power consumption has become a key limitation for high-speed, high-data-rate electronic systems. To address power limitations, advanced techniques and methodologies are being applied to chip designs that consume less power while maintaining the frequency required for high-performance operations. In addition to the widely used gated-clock approach, low power design techniques such as the use of multiple Vth transistors, multiple voltage domains, power gating, and dynamic back-biasing are rapidly being adopted. However, the use of these techniques creates a major challenge in physical power integrity analysis and verification.
Unlike static-only or pseudo-dynamic approach to power grid verification, RedHawk-SDL's full-chip transient simulation (time-point by time-point) identifies critical issues for low power designs. RedHawk-SDL's new release will support design techniques based on multiple Vth and multiple Vdd domains, and header/footer switches.
RedHawk-SDL accurately simulates power-supply noise waveforms based on simultaneous switching events and full-chip power-grid parasitics. Clearly, designers need to understand and resolve the impact of dynamic noise on a chip's timing requirements. RedHawk-SDL's impact to timing flow addresses the timing accuracy from cell delay characterization and simulation based on actual P/G noise waveforms. RedHawk's ATR (Apache Timing Report) provides rankings of noise-susceptible instances and / or paths.
At the full-chip level, RedHawk-SDL provides effective Vdd for each instance over its switching timing window, or modified SDF (MSDF) for sign-off timing analysis tools. The full-chip feedback provides accurate screening of paths with high timing risks.
Apache's flagship RedHawk-SDL fills the critical missing link for physical power flows in 130nm, 90nm, and 65nm SoC designs. It provides the only full-chip static and Vectorless DynamicTM physical power solution that is capable of addressing dynamic power issues such as simultaneous switching outputs (SSO) for core, memory, clock and I/O, as well as the effects of on-chip inductance, package models, and decoupling capacitance.
Enhancements to RedHawk-SDL for low power designs and impact to timing flow will be available in Q3.
By providing tools for power, timing, and system I/O integrity, Apache enables leading networking, wireless, communication, consumer, and semiconductor companies to develop highly competitive and reliable products. Apache's physical design integrity products are used early in the sub-130 nanometer design process with minimal setup, delivering the highest standards of computational performance, capacity handling, and integrity. For more information, including a white paper on dynamic analysis, visit http://www.apache-da.com
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