CIMdata PLM Industry Summary Online Archive
31 May 2004
Implementation Investments
Siemens Adopts Mentor Graphics Catapult C Synthesis Tool for 50 Percent Reduction in RTL Implementation of C Algorithms
Mentor Graphics Corporation announced that Siemens Information and Communications Networks (ICN) has reduced C source to register transfer level (RTL) implementation time by 50 percent on a strategic project using the new Mentor Graphics® CatapultT C Synthesis tool. As a result, Siemens ICN has adopted the tool, which will be used by the Munich-based design team to develop an application-specific integrated circuit (ASIC) for a voice over IP (VoIP) application.
"We were impressed by the results. The fact that we could synthesize our untimed, system-level C/C++ source code with minimal modification played an important role in the success of this project. It provided a precise path from our system-level models all the way to RTL, which allowed us to meet our required design goals in significantly less time," said Rudolf Krumenacker, vice president, system-on-chip design, Siemens ICN. "Mentor Graphics field and product teams provided us with excellent support, enabling us to apply-in only a few days-this new technology to our highly important project."
Using the Mentor Catapult C Synthesis tool, Siemens' design team discovered that it could automatically generate correct RTL for a complex VoIP algorithm in half the time required with conventional manual methods. The synthesized RTL code readily met placement and routing timing, while satisfying the project's latency requirements.
The Catapult C Synthesis tool is the only high-level synthesis tool that automatically generates error-free RTL hardware descriptions from system-level, un-timed C/C++ code-up to 20 times faster than traditional manual methods. The Catapult C Synthesis tool also allows designers to perform detailed exploration, or "what-if" analysis, on varying micro-architecture and interface scenarios in order to fully optimize designs. Uniting system-level and hardware design, the tool targets ASIC and field-programmable gate array (FPGA) designers who are designing complex devices for next-generation applications, including digital signal processing (DSP), used in wireless and satellite communications, as well as video and image processing.
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