CIMdata PLM Industry Summary Online Archive
1 June 2004
Implementation Investments
Ambarella Selects @HDL
@HDL, Incorporated ( http://www.atHDL.com ) announced that Ambarella is now incorporating @HDL products for the development of an advanced technology System-on-Chip (SoC) design. Ambarella Incorporated, based in Sunnyvale, California, is a fabless semiconductor company focusing on next generation consumer digital media applications and is funded by a first tier global venture capital firm. Both the @Verifier and @Designer products have been deployed throughout the Ambarella hardware engineering team since their SoC project inception earlier this year.
"We initiated our search for leading edge functional verification tools with the specific goal of selecting the vendor that could help deliver the debug productivity and functional verification completeness demanded by our aggressive SoC design specs. Our team selected @HDL as we see the @Designer and @Verifier products shortening the time to detect, isolate and correct RTL errors very early in our development process," stated Chan Lee, Ambarella Vice President of VLSI Engineering. "The powerful analysis capabilities of @Designer will allow our design and verification engineers to more rapidly debug their simulation results and will provide for a smooth and effective transition to assertion-based functional verification."
The @Verifier and @Designer products from @HDL have demonstrated to be effective in accelerating the task of functional verification for leading-edge SoC and ASIC design teams worldwide. Notable @HDL installations include Cisco, Raza Microelectronics, Renesas and Toshiba, which have seen significant verification productivity improvements in their projects.
@Designer delivers an extensive feature set to improve RTL and gate-level debugging of simulation results. With its advanced support for design, assertion and testbench debugging, it has emerged as the technology leader in graphical debugging, working in conjunction with the most widely used logic simulators, including ModelSim, NC/Incisive, and VCS. Powerful debug features available beyond those traditionally provided by other vendors include incremental cone viewing and refinement with value annotation, automatic mnemonic extraction and display, expression viewer, execution tracing and memory content tracing and break-pointing without explicit dumping of memory contents.
The @Verifier includes @Verifier-DP for distributed processing on existing simulation server farms and @Verifier-ZX, adding the powerful formal solvers based on the IBM RuleBase technology. @Verifier helps designers and verification engineers to find bugs earlier in the design cycle by incorporating some of the latest advancements in technologies ranging from formal solver algorithms, to design and space reduction techniques, and extensive support for multiple clock domain verification and analysis.
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