CIMdata PLM Industry Summary Online Archive
1 June 2004
Implementation Investments
Azul Deploys @HDL Functional Verification
@HDL, Incorporated announced that Azul Systems is now incorporating @HDL products for the development of an advanced technology chip design. Azul Systems is a venture-backed, pioneering technology company focused on specialized data center infrastructure, located in Mountain View, California. Both the @Verifier and @Designer products have been deployed throughout the Azul hardware engineering team since project inception.
"Our team carefully investigated the vendors in the functional verification area, looking especially for tools that could significantly reduce our simulation debug time and raise our overall verification productivity. We selected the @HDL family of products and have been very satisfied with their overall functionality and excellent technical support. The powerful simulation oriented graphical debugging analysis capabilities of @Designer combined with the automatic assertion extraction and clock analysis features of @Verifier have allowed our team to f ind more bugs earlier in the RTL development stages," stated Scott Sellers, Vice President of Hardware Engineering, CTO and co-founder of Azul.
The @Designer and @Verifier products from @HDL are effective in accelerating the task of functional verification for leading-edge SoC and ASIC design teams worldwide. Notable @HDL installations include Cisco, Raza Microelectronics, Renesas and Toshiba, which have seen significant verification productivity improvements in their SoC and ASIC projects. @Designer delivers an extensive feature set to improve RTL and gate-level debugging of simulation results. With its advanced support for design, assertion and testbench debugging, it has emerged as the technology leader in graphical debugging, working in conjunction with the most widely used logic simulators, including ModelSim, NC/Incisive, and VCS. Powerful debug features available beyond those traditionally provided by other vendors include incremental cone viewing and refinement with value annotation, automatic mnemonic extraction and display, expression viewer, execution tracing and memory content tracing and break-pointing without explicit dumping of memory contents.
The @Verifier family includes @Verifier-DP for distributed processing on existing simulation server farms and @Verifier-ZX, adding the powerful formal solvers based on the IBM RuleBase technology. @Verifier helps designers and verification engineers to quickly find bugs earlier in the design cycle by incorporating some of the latest advancements in technologies ranging from formal solver algorithms, to design and space reduction techniques, and extensive support for multiple clock domain verification and analysis.
@HDL delivers an effective assertion-based verification product suite to its customers, including such companies as AMD, Cisco, Fujitsu, OKI Semiconductor, SiNett, Raza Microelectronics, Renesas and Toshiba.
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