CIMdata PLM Industry Summary Online Archive

1 June 2004

Product News

Bluespec Inc. Announces General Availability Of Bluespec Compiler And Bluespec Simulator

Bluespec Inc. ( http://www.bluespec.com ) announced general availability of its SystemVerilog-based Electronic Design Automation (EDA) toolset that creates a new level of abstraction for ASIC and FPGA engineers to control the growing design complexities involved with large-scale digital systems designs. In limited release since January 2004, the toolset enables for the first time high-level hardware synthesis with Quality of Results (QoR) that match hand-coded Register Transfer Level (RTL), accelerating the time to a verified netlist by as much as 50 percent and dramatically reducing verification efforts.

The toolset wraps SystemVerilog around Term Rewriting Systems (TRS)-based synthesis, a technology developed at Massachusetts Institute of Technology (MIT) that enables control logic generation on a correct-by-compiler construction basis. The combination allows engineers to raise the level of abstraction in design of ASICs and FPGAs while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. Bluespec further accelerates the overall product development cycle by delivering from a single high-level source both the RTL and a cycle-accurate C model that can be used for system level verification.

With a much higher level of design abstraction and the capability to generate both RTL and C, Bluespec offers a new design paradigm using SystemVerilog and assertion-based design. Designers have the option of working at different levels within the same environment: from transaction level simulation and debug down to a specific hardware implementation. A higher level of abstraction also ensures no premature freezing of architectural choice and allows more rapid timing closure. For the first time, Bluespec offers a unified design environment where designs can be architected, modeled, rapidly evaluated, and hardware generated.

Bluespec's tools sit directly in front of current design flows. The designer specifies the implementation at a high-level as System Verilog design assertions and generates Verilog output or cycle accurate C. Bluespec is completely interoperable with Verilog-based designs. Bluespec can easily incorporate Verilog IP - alternatively, Bluespec can be used within Verilog implementations. The toolset consists of two components: Bluespec Compiler and Bluespec Simulator.

Bluespec Compiler (BSC) includes the following compiler capabilities:

•  SystemVerilog language with Bluespec design assertions

•  Correct-by-compiler construction of control and datapath logic

•  Generation of no-compromise Verilog 95 RTL

•  Integrated, comprehensive static verification of designs to eliminate problems before simulation

•  Code succinctness and static elaboration for high-level abstractness and 10:1 code compression for large designs

•  Integrates existing Verilog IP and easily integrates into Verilog designs

•  Simplifies the integration of IP and creation of high-reuse IP

•  Rich library of design building blocks

•  Integrated compiler algorithms and techniques:

•  Modular compilation and design

•  Automated and user-defined scheduling of hardware

•  Scheduling visualization and feedback

•  Resource assignment, optimization

•  Standard optimizations, including common sub-expression elimination and logic

Bluespec Simulator (BSIM) includes the following simulation capabilities:

•  Cycle accurate C-based simulation of the high-level design

•  100% cycle accurate with Verilog

•  Full visibility to Bluespec source, interfaces, state elements and design assertion rules

Both tools are designed and tested to work on Linux Red Hat versions 7.2 and 8.0.

The toolset is shipping now.

 

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