CIMdata PLM Industry Summary Online Archive
1 June 2004
Product News
Cadence Encounter Platform Supports Virage Logic Structured-ASIC Design Libraries
Cadence Design Systems, Inc. and Virage Logic Corporation ( http://www.viragelogic.com ) announced support for both Area, Speed and Power (ASAP) LogicT structured-ASIC Metal Programmable and Standard Cell Libraries within the Cadence® EncounterT digital IC design platform. This leverages the capabilities of SoC Encounter's IC implementation in the structured array, as well as standard cell markets. Further, it enables mutual customers to make trade-offs between density, cost and performance according to their requirements. This capability is deployed with SoC Encounter 3.3, in production now.
"Cadence ( http://www.cadence.com ) support of Virage Logic's structured-ASIC libraries provides a real advantage to customers," said Lavi Lev, Cadence executive vice president and general manager. "It expands our industry-leading support in this critical emerging marketplace from traditional ASIC vendors to COT customers, who now can enjoy the benefits of the structured-ASIC approach within the integrated RTL-to-GDSII design environment of SoC-Encounter."
ASAP Logic products contain application-optimized libraries targeted to unique market requirements and are based on Virage Logic's proprietary and patented routing methodology and cell architecture. ASAP Logic Metal Programmable Cell Libraries are used in System-on-Chip (SoC) designs to economically enable functional reprogrammability by changing only a few metal and via masks. ASAP Logic Standard Cell Libraries are optimized for area, speed, and power and provide up to a 30 percent increase in utilization when compared to conventional standard cell libraries.
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