CIMdata PLM Industry Summary Online Archive
1 June 2004
Implementation Investments
Faraday Adopts Incentia for ASIC Synthesis & Timing Flow
Incentia Design Systems, Inc. announced that Faraday Technology Corporation has successfully integrated Incentia's software into its ASIC synthesis and timing flow.
"Because our benchmark showed Incentia's logic synthesis and timing analysis software successfully reduced chip area and greatly shortened run time, we were confident about adopting Incentia's tools into our ASIC flow," said Jim Wang, director of the Design Development Division at Faraday. "Our real design examples showed that Incentia's software achieved high performance and facilitated our customers' projects."
Faraday joined Incentia's LibCraftT Library partner program in 2001. By integrating Incentia's synthesis and timing tools, Faraday delivers comprehensive ASIC libraries with robust performance.
Incentia offers three major products for synthesis and timing analysis. TimeCraft® is a full-chip, gate-level static timing analyzer, offering fast analysis speed for timing sign-off and Engineering Change Orders (ECOs). DesignCraft® is a logic synthesis tool with datapath, test and low power options. DesignCraft ProT is a physical synthesis tool that solves timing closure issues and shortens turnaround time. All products are based upon a unified timing engine and database and address the ever growing design requirements of speed, performance and capacity.
Faraday Technology Corporation is a silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, high speed I/Os. With more than 500 employees and 2003 revenue of $111 million, Faraday is the largest fabless ASIC company in the Asia-Pacific region. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com
Incentia Design Systems, Inc. ( http://www.incentia.com ) is a provider of logic and physical synthesis and timing software that addresses the stringent requirements of runtime, design capacity, timing, area, Design for Test (DFT), power consumption, and signal integrity for multi-million-gate SoC designs.
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