CIMdata PLM Industry Summary Online Archive
2 June 2004
Implementation Investments
NEC Selects Verific Design Automation HDL Component Software
Verific Design Automation announced that NEC's System Devices Research Laboratories has purchased a license of its HDL Component Software.
"NEC spends significant resources in advancing state-of-the-art EDA research to maintain its leadership position in SOC design," says Dr. Masao Fukuma, vice president and general manager of NEC System Devices Research Laboratories. "Using Verific's software fits right into our best-in-class strategy."
NEC enhances the capability of its cutting-edge C-based system-on-chip (SoC) design environment where Verific's VHDL, Verilog 2001 and other related software will act as a front-end for NEC's (SoC) design environment. NEC received source code for VHDL and Verilog parsers, analyzers, and elaborators, as well as a register transfer level (RTL) database. The Verific software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms.
"We very much liked that Verific provides us with source code," adds Dr. Katsuharu Suzuki, NEC's technical lead. "In addition, support and training so far have been excellent."
Verific Design Automation was founded in 1998 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based Verilog and VHDL front ends-parsers, analyzers and elaborators-as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 20,000 end-user copies. Website: http://www.verific.com
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