CIMdata PLM Industry Summary Online Archive

5 June 2004

Product News

eASIC® and Golden Gate Technology Announce the Adoption of Critical EDA Software to Support Structured ASIC Design

eASIC® Corporation ( http://www.eASIC.com ), a provider of Structured ASIC technology and products, and Golden Gate Technology, a developer of power driven physical design tools, announced the adoption of two products from Golden Gate's GoPower suite. The IC-PlanT and PowerPlacerT tools will be used for eASIC's Structured eASIC array. With this cooperation, the partners will incorporate Golden Gate's clock aware physical design into eASIC's tools set for Structured ASIC, responding to the market requirements of less power consumption, reduced wire length and guaranteed routability. As part of the agreement, two of Golden Gate's products, the advanced power managing floorplanner (IC Plan) and the advanced power reducing placer (PowerPlacer), will be integrated into eAISC's tools kit for designer's use.

"Golden Gate's physical design tools are very important for addressing today's deep submicron ASIC design challenges," said Zvi Or-Bach, eASIC President and CEO. "After evaluating the tools, eASIC was very impressed with the Golden Gate's PowerPlacer quick run-time, reduced wire length and superior routability. We found it is a perfect match for our customer's needs. Using Golden Gate's floorplanner helps us in providing design-friendly Structured ASIC, which is NRE-free, removing design-entry barrier and allowing low-cost and high performance ASIC. This integration of powerful EDA tools and innovative technology allows us to create a comprehensive Structured eASIC offering from RTL to complete physical design."

Production release of the Structured eASIC tools set is slated for Q4 CY 04.

Golden Gate Technology Inc. was founded in 2001 with the goal of building power driven physical design tools targeting very deep submicron system-on-chip circuits.

 

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