Optimal Products Selected by TSMC for Integrated Chip-to-Package Co-Design in TSMC Reference Flow 5.0

CIMdata PLM Industry Summary Online Archive

7 June 2004

Product News

Optimal Products Selected by TSMC for Integrated Chip-to-Package Co-Design in TSMC Reference Flow 5.0

Optimal Corporation ( http://www.optimalcorp.com/ ), a provider of signal integrity design simulation, extraction and analysis tools serving the semiconductor industry, became a key player in the first-ever integrated chip and package co-design methodology for the foundry industry as a part of Taiwan Semiconductor Manufacturing Company's (TSMC's) ( http://www.tsmc.com ) Reference Flow 5.0. (NYSE:TSM) (TSE:2330).

Optimal has contributed three tools to TSMC's Reference Flow 5.0 that provide power and timing closure at the IC and package co-design phase. PowerGrid-DC addresses IR drop, current density and SPICE netlists while PakSi-E and SIDEA are used to extract package parasitics and generate timing information in SDF (standard delay format). Together with other features of Reference Flow 5.0, they make up the foundry industry's first integrated chip-and-package design methodology and play a key role in the foundry industry's first power closure capability.

"As we geared up to handle the next generation of system-on-chip designs, it became clear that power closure would become a dominant technical issue," said Edward Wan, Senior Director of Design Services Marketing for TSMC. "The ability to provide power closure through to the package design increases the reliability of the design, greatly enhances the design experience and accelerates time-to-market."

Dr. An-Yu Kuo, Co-Founder and Chief Technical Officer for Optimal stated, "We're glad to be working with TSMC in the development of its first IC-to-package co-design methodology. Clearly, as wireless communications and consumer end products require higher and higher current or speed, power and timing closure become essential issues for meeting time-to-market requirements.

Kuo continued, "TSMC acutely recognized this upcoming verification trend as it planned its next generation reference flow and we are pleased that Optimal was selected as a co-development partner in this venture. We look forward to working with TSMC on the joint development of future design technologies."

Reference Flow 5.0 recognizes the need for power-aware, integrated IC and package design. In particular, it addresses two important design integrity issues for both IC and package design that are becoming increasingly problematic at 90 nanometers and below. These issues are power closure and timing closure.

In the past, the current entering a semiconductor device was relatively low, so the resistance created by a chip's package (IR drop) was approximated and handled through package and lead selection. Today, design teams must contend with very high currents. In this environment, a package resistance can cause voltage drops severe enough to upset a 1-volt design. The design team must ensure compatible power distribution both on-chip and in the package.

TSMC Reference Flow 5.0 architects recognized that achieving this level of design assurance would require a new methodology. This methodology, co-developed by Optimal and TSMC, is described below:

1. Optimal's PowerGrid-DC provides an equivalent resistive SPICE netlist among the solder bumps (or bondwires) and solder balls. This SPICE netlist is imported as a loading condition into third-party on-chip tools to perform IR drop analysis. The interaction between the chip and package is then accounted for automatically.

2. Third party on-chip tools provide the current loads through every solder bump (or bondwire) and PowerGrid-DC computes the voltage and current density at every location (including the solder bump/bondwire) in a package. With PowerGrid-DC, it is immediately known whether there are hot spots where the current density exceeds some threshold or whether the power distribution layout (power planes, vias, solder balls and bondwires) can support the correct voltage to the chip.

Due to space constraints, the signal trace routing on a package tends to have multiple lengths. For example, the signal traces routed to the corner of a package are typically longer than those routed to the edge of a package. Such differences among trace lengths must be compensated for on the PCB (for example, for source-synchronous, parallel bus designs). An automated design flow is needed to quantify the timing delay from the I/O circuitry to the package pins (so that proper trace compensation can be made on the PCB).

Users of TSMC's Reference Flow 5.0 can co-design their IC and package by using Optimal's PakSi-E and SIDEA to extract the package parasitics and generate timing information in standard delay format (SDF). This information is provided as a loading condition to third party on-chip tools that extract the I/O circuitry, extract redistribution layer parasitics and perform static timing analysis, all the way from chip I/O to the package pins (or solder balls). Such IC and package co-design allows system or board designers to automate the routing adjustment on the PCB.

PowerGrid, PakSi-E, and SIDEA are available immediately for Microsoft Windows. List prices start at $35,000 per license.

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