CIMdata PLM Industry Summary Online Archive
8 June 2004
Product News
Altera Collaborates with Synopsys on Hardcopy Structured ASICS
Synopsys, Inc. ( http://www.synopsys.com ) and Altera Corporation announced an agreement for the establishment of Synopsys Professional Services resources to support the HardCopy® design center. This agreement is driven by the growing demand for HardCopy devices in the marketplace. The collaboration will accelerate HardCopy device implementation by establishing an advanced and optimized back-end design flow and provide access to expert physical design resources that will complement Altera's existing HardCopy design center. Additionally, designers can now use Synopsys' GalaxyT Design Platform front-end flow to design their Stratix FPGA.
The agreement builds on work already in progress for the development of a new timing-driven HardCopy back-end design flow based on Synopsys' Galaxy Design Platform and optimized for Altera's FPGA-to-HardCopy migrations. The flow will be used by Altera and Synopsys to further optimize the chip performance and reduce the turn-around-time of HardCopy implementations. Once a customer's design is verified in a Stratix® FPGA, the Altera HardCopy Design Center performs the necessary back-end design services required to build production masks. Based on Synopsys Professional Services' many years of experience in implementing FPGA and ASIC designs, Altera will utilize Synopsys as complementary design resources to support these implementation efforts. Services performed will include place-and-route, design rules checking, formal verification, and the generation of the final GDSII artwork. Using the Synopsys Galaxy flow helps Altera deliver fast and predictable turnaround times to HardCopy users.
Customers can now target Altera Stratix FPGAs and HardCopy devices with the front-end Galaxy design platform, which includes Design Compiler® (DC) FPGA, DesignWare®, Formality®, and PrimeTime®. DC FPGA allows designers to design once at the RTL for the FPGA or HardCopy structured ASIC. Designers can then reuse their source description, synthesis scripts, constraint files and DesignWare IP to migrate the design from FPGA to a HardCopy Structured ASIC or a standard cell ASIC.
Altera's use of Synopsys' Galaxy solution provides for fast turnaround times for the migration of Stratix FPGAs to HardCopy Structured ASICs. The HardCopy design flow utilizes Star-RCXTT for parasitic extraction with PrimeTime for static timing analysis, PrimeTime SI for signal integrity analysis, DFT CompilerT for the test circuit synthesis in combination with TetraMAXT for the test pattern generation, and AstroT for the HardCopy device place and route.
Altera's HardCopy Stratix devices offer a seamless migration path from an FPGA prototype to a low-cost mask-programmed device. Accessible through Altera's Quartus® II software, HardCopy devices deliver ASIC-level performance, price, and features that customers can take to production risk-free. HardCopy Stratix devices have the same features as the successful Stratix FPGAs and offer an average 50 percent performance increase. HardCopy devices also consume up to 40 percent less power compared to the equivalent Stratix FPGAs. Altera's HardCopy Stratix devices are ideal for high-performance, high-volume applications in the storage, networking, wireless communication, consumer electronics, and industrial markets. For more information about HardCopy Stratix devices, please visit http://www.altera.com/hardcopystratix
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