CIMdata PLM Industry Summary Online Archive
8 June 2004
Product News
Forthcoming Upgrade to Analog/Mixed-Signal IC Layout Tool Speeds Verification by up to 22 Percent; Tanner's L-Edit v11.1 Node Highlighting Premiering at DAC
Tanner EDA ( http://www.tannereda.com ), a division of Tanner Research , is demonstrating a key upgrade to its L-Edit Pro analog/mixed-signal layout tool for IC design at DAC 2004.
The new node highlighting function allows users to point to an object in the layout, regardless of hierarchy, and display all the geometry connected to it based on its set of connectivity rules. For example, the connectivity rules for metal layers can be applied and a node highlighted by selecting Metal 1 geometry. Where layout vs. schematic verification (LVS) is being performed, discrepancies between the schematic netlist and the extracted netlist are highlighted in the layout, enabling the differences to be rapidly identified and debugged. Increase in design size is inversely proportional to decrease in verification time, with larger designs showing processing speed improvements of up to 22%.
Although DRC debugging often takes more total time in the design process, LVS debugging is usually more complicated, with each individual fix taking a relatively long time. Node highlighting in L-Edit v11.1 improves design productivity significantly during LVS. For example, when the LVS indicates an open circuit between two nodes, the nodes can be highlighted to determine where they are in close proximity-the most likely point at which a connection may have been intended. Where accidental short-circuits occur, highlighting the node incrementally helps determine where the crossover to another node occurs. The tool can also identify the shortest path between two nodes, help with visual analysis of crosstalk, and carry out certain signal integrity checks.
L-Edit Pro v11.1 will be available from July 1, 2004, priced at $16,500 for a single user license.
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