CIMdata PLM Industry Summary Online Archive
28 June 2004
Product News
Sonics Integrates Smart Interconnect IP With Cadence and CoWare Electronic System-Level (ESL) Design-For-Verification Flow
Sonics, Inc. announced that the company has joined Cadence Design Systems, Inc. and CoWare, Inc. in supporting the Cadence/CoWare integrated, flow for electronic system-level (ESL) design through verification for complex SoC designs. The flow is based on tight integration between CoWare's SystemC-based ConvergenSCT SoC design tools, the ConvergenSC Model Library and the Cadence IncisiveT functional verification platform. Into this flow, Sonics adds its SMART Interconnect IPT that integrates multiple IP blocks into working silicon and its SonicsStudioT interconnect IP configuration tool. This completes the concept-to-silicon vision with tight integration to a wide array of hardware IP.
Time to verification and time to global timing closure are the two issues delaying rapid development of complex SOCs. The CoWare/Cadence ESL design flow reduces the time to verification by 50%. The addition of Sonics IP reduces the time to global timing closure by 50%.
System Timing Closure
Today, critical timing paths within complex SoCs are not known until the physical prototyping stage, when actual interconnect becomes available. Only from this point can timing closure be addressed, often resulting in complete architectural redesign. Using Sonics Interconnect IP brings those physical timing constraints to the system design level and, using SonicsStudio, injects them into the Cadence/CoWare ESL flow.
The link between SonicsStudio and the Cadence/CoWare design-to-verification flow is through the exchange of automatically generated SystemC transaction level models of the entire SoC including configured interconnects.
Sonics Closes Links to the Physical Domain
Further integrating the ESL flow to the physical domain, Sonics has enabled the importation of LEF/DEF files from Cadence's EncounterT digital IC design platform. This enables the designer to directly compare the floor plan connections with the physical connections of the SMART Interconnect IP. This abstracted, but physically accurate view of the SoC now gives the designer the ability to find and correct architectural flaws in the first days or weeks of design instead of the final months.
Sonics provides an essential link to the myriad of third party and internally developed IP blocks that are needed to construct complex, multimillion gate SoCs. Its SMART Interconnect IP connects complex IP blocks such as microprocessors, DSPs, hardware accelerators such as MPEG, DMA or packet processors with any other IP block with a high degree of silicon efficiency and high data throughput.
Sonics and CoWare will streamline and optimize the interoperability between Sonics SMART Interconnect IP, SonicsStudio and CoWare's ConvergenSC platform. Sonics Studio is a comprehensive suite of SOC integration, IP configuration, logic verification tools and utilities. Users of SonicsStudio and ConvergenSC will now share interoperable SystemC models and enjoy interoperability with the largest SystemC model library.
"Now, customers of Sonics, CoWare and Cadence can rapidly interact with their design at the ESL design level with confidence that their architectural decisions will be reflected directly down to the physical SoC integration level," said James Colgan, director of marketing at Sonics, Inc.
For more information about CoWare and its products and services, visit http://www.coware.com
For more information about Sonics, Inc., see http://www.sonicsinc.com
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