CIMdata PLM Industry Summary Online Archive
13 July 2004
Implementation Investments
Atmel Adopts Cadence Virtuoso UltraSim FastSPICE Simulator for Verifying Complex Mixed-Signal Designs
Cadence Design Systems, Inc. ( http://www.cadence.com ) announced that Atmel's Radio Frequency (RF) design group has adopted the Virtuoso® UltraSim Full-chip simulator to verify complex mixed-signal designs targeted at wireless consumer electronics, PC peripherals and industrial control applications.
"Integrating the Virtuoso UltraSim simulator for full-chip verification into our existing Virtuoso Spectre-based ZigBeeT transceiver design flow was surprisingly straightforward," said Tim Hersh, RF design engineer at Atmel. "The Virtuoso UltraSim simulator reads in the same Spectre netlists and models and uses the same equations, guaranteeing close correlation in results. We were able to increase our productivity by five times. On a second design containing 300,000 transistors and parasitic components, we were able to run the simulation in record time, which was previously either a challenge or sometimes even impossible with circuits of this size and complexity using other simulators. The Virtuoso UltraSim simulator gives us greater confidence in our designs, as it ensures first-pass silicon success."
The Virtuoso UltraSim simulator, the cornerstone of the Cadence Virtuoso custom design platform and an integral part of Virtuoso Multi-mode Simulation, uses next-generation technology based on advanced matrix and model acceleration techniques to achieve high speeds and capacity, while maintaining silicon accuracy for even the toughest analog and RF circuits. It also provides designers with the performance required for post-extraction verification of full-chip designs. These features enable designers to accelerate verification cycles, improve productivity and shorten time-to-market.
The Atmel ZigBee ready transceiver design is based upon the company's AT46k 0.35 micron SiGe BiCMOS process. This is a complete transceiver designed to transmit and receive the direct-sequence spread spectrum BPSK modulated digital data over the European (868 MHz) and American (902 to 928 MHz) frequency bands. The transceiver supports the ZigBee 40 kBPS data rate and can spread and despread the data at the ZigBee standard chip rate (600 kCPS). The chip provides its own bandgap references, VCO, Fractional-n Synthesizer, and an on-chip system frequency reference oscillator. Configuration and control is provided via a digital serial interface (SPI) which can be easily interfaced with the Atmel Z-LinkT microcontroller that is customized for 802.15.4 and ZigBee systems. The receiver and its associated peripheral circuitry, which normally took days to simulate, was simulated in less than five hours with Virtuoso UltraSim.
Virtuoso UltraSim is the Cadence FastSPICE simulator that addresses the need for speed, capacity, design abstraction and accuracy when verifying designs or systems. Virtuoso UltraSim is an integral part of Virtuoso Multi-mode Simulation, providing all the simulation components necessary for validating an IC or system.
Virtuoso Multi-Mode Simulation offers a combination of SPICE, FastSPICE, AMS, and RF simulation in a flexible single multi-mode simulation licensing scheme. All Virtuoso simulators-Virtuoso Spectre, Virtuoso UltraSim and Virtuoso AMS Designer-support common syntax and models, and share equations ensuring silicon accurate results.
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