CIMdata PLM Industry Summary Online Archive
19 July 2004
Product News
Mentor Graphics Introduces the Industry's First Concurrent Chip-to-Board Solution for FPGA and PCB Design
Mentor Graphics Corporation announced I/O DesignerT, a new solution that facilitates concurrent chip-to-board design of field-programmable gate arrays (FPGAs) and the PCB. Part of Mentor's continued effort to support electronics companies' need to capitalize on the latest advances in PCB and FPGA technology, the solution allows bi-directional communication and data management throughout the process of implementing complex FPGAs on to the PCB. In product case studies, by managing the FPGA and PCB design concurrently, I/O Designer allowed users to reduce the total PCB route lengths by more than 15 percent, resulting in fewer routing layers, significantly reducing design time, optimizing system performance and lowering product manufacturing costs.
"As the only EDA tool provider in the industry with expertise in both PCB and FPGA design, Mentor Graphics is the first to offer solutions for integrating these once separate design processes. I/O Designer allows PCB designers more control early in the design process, ensuring maximum productivity for the entire systems design team," said Henry Potts, vice president and general manager, Systems Design Division, Mentor Graphics. "Integrating FPGA and PCB design processes is no longer just an important way to improve efficiency-it has become imperative to ensure system performance and lower product costs."
The I/O Designer solution provides for concurrent design of the FPGA and PCB by bridging these design environments and automating the various processes needed to implement today's high pin-count, high-speed FPGAs on to complex PCBs. Starting with early hardware description language (HDL) descriptions of the FPGA, I/O Designer's automated schematic symbol generation function provides PCB designers the schematic symbols used to represent FPGAs in the PCB design. Then I/O Designer incrementally and bi-directionally manages pin assignments on the FPGA by:
• Graphically assigning signals to designated pins in a guided FPGA library environment;
• Constraining pin mapping pre-synthesis to achieve optimal FPGA and PCB interconnect;
• Communicating allowable FPGA pin-swaps to the PCB solution;
• Synchronizing pin-out assignments between the FPGA and PCB solutions for rapid timing closure and routing completion;
• Communicating constraints between the PCB and FPGA solutions;
• Allowing designers to optimize their I/O Design for PCB layout.
"With I/O Designer, our team has eliminated hours of time previously spent manually checking and double-checking the FPGA pinlist," said Arie Doorduin, electronic design engineer, Research and Development, Astron. "With I/O Designer there is a clear, consistent relationship between the pin assignment of the schematic and the synthesis tool. As a result, absolutely no checking is required."
Pricing and Availability
I/O Designer is available immediately with pricing starting at US$10,000. I/O Designer integrates Board Station®, ExpeditionT and PADS® with the Mentor Graphics FPGA Advantage® integrated flow as well as design tools from major programmable logic vendors. More information can be found at http://www.mentor.com/expedition/io_designer.html
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