CIMdata PLM Industry Summary Online Archive
19 July 2004
Product News
Synopsys' New PCI Express PHY IP Enables Lower Cost ICs
Synopsys, Inc. announced the availability of its DesignWare® PCI ExpressT Physical (PHY) layer intellectual property (IP), which rounds out a complete PCI Express Endpoint IP solution. Based on Synopsys' silicon-proven 6.25 Gbps backplane and high-speed SERDES (serializer-deserializer) technology, the DesignWare PCI Express PHY is optimized to be half the size, with twice the sensitivity and twice the jitter margin as competing solutions. These characteristics enable higher yield, better interoperability, lower field returns and ease-of-use in end applications. By combining the new PHY with its PCI Express digital controller core and verification IP, Synopsys is offering designers a low-risk, integrated digital and mixed-signal IP solution for PCI Express applications.
As high-volume products are beginning to require PCI Express functionality, designers are looking to embed both the digital core and mixed-signal PHY in their SoCs to reduce cost. Examples of PCI Express applications include high-speed graphics, video-enabled peripherals, along with other hardware connecting to PCs using Intel's recently released Grantsdale chip set.
Pricing and Availability
The DesignWare PCI Express PHY is available now for early adopters. Contact Synopsys for pricing information. Also available now are the DesignWare PCI Express Verification IP and Endpoint Controller core. Synopsys Professional Services offers high speed signaling expertise to help system and chip designers with their packaging and board designs.
For more information on DesignWare IP, visit: http://www.designware.com or call 1-877-4BEST-IP.
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