CIMdata PLM Industry Summary Online Archive
20 July 2004
Product News
Tower Semiconductor Selects Virage Logic's Semiconductor IP for 0.13-Micron Offering
Tower Semiconductor, an independent wafer manufacturer, and Virage Logic Corporation ( http://www.viragelogic.com ) have signed a licensing agreement under which Virage Logic's Technology-Optimized Platforms will be made available on Tower's 0.13-micron CMOS processes.
Under the terms of the agreement, Tower customers can access Virage Logic's Technology-Optimized Platforms-comprising highly differentiated, silicon-proven embedded memories, standard cell logic libraries and I/O libraries-on Tower's 0.13-micron TS13SL (standard logic) process, followed by support for its 0.13-micron TS13LP (low power) process. In addition, Tower customers will have access to Virage Logic's rich portfolio of highly differentiated IP including the Self-Test and Repair (STAR) Memory SystemT and the patented Area, Speed and Power (ASAP) LogicT Metal Programmable Cell Libraries. Because of the longstanding partnership between the two companies, Virage Logic was given early access to Tower's process and significant elements of the Virage Logic Technology-Optimized Platforms are already silicon-proven on Tower's 0.13-micron process.
"We selected Virage Logic because of our mutual success in previous technology generations, silicon-proven libraries on our process and their commitment and focus on delivering highly differentiated IP," noted Doron Simon, president, Tower USA Inc. "As we introduce our 0.13-micron offering, it is critical that we work with a partner that has experience in advanced process technologies. Our growing worldwide customer base can now gain a competitive advantage in terms of cost and performance."
"We are pleased to extend our successful partnership with Tower to include support of Tower's most advanced technologies in its world-class fab with our Technology-Optimized Platforms," said Adam Kablanian, president and chief executive officer of Virage Logic. "In addition, with access to the STAR Memory System, which substantially reduces test costs and improves overall yield, and our patented ASAP Logic Metal Programmable libraries, which save configuration costs by reprogramming only a few masks, Tower's customers can realize significant savings and achieve a shorter time-to-volume."
Virage Logic's Technology-Optimized Platforms, which are custom-tuned to a target manufacturing process, aim to meet the critical requirements of reducing design time, silicon area and design risk, while boosting performance and enhancing manufacturing yields. By providing silicon-proven, fully characterized IP that is tuned to all major electronic design automation (EDA) design tools and flows, Virage Logic's Technology-Optimized Platforms address the needs of complex and mainstream System-on-Chip (SoC) designs.
Availability
Front-end views for Virage Logic's Technology-Optimized Platforms for Tower's 0.13-micron process are expected to be available by Q3 2004.
Tower Semiconductor LTD. is a pure-play independent wafer foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 micron; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. The Tower Web site is located at http://www.towersemi.com
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