CIMdata PLM Industry Summary Online Archive
16 August 2004
Product News
Novas Extends SystemVerilog Support Across Product Line with New nLint Release
Novas Software, Inc. continues to drive support for the Accellera SystemVerilog standard with hardware description language analysis (also known as linting) that builds on existing support for the language across the Company's debug solutions. The Novas nLintT tool now provides basic rule-checking capabilities for all SystemVerilog 3.0 design constructs to enable the early detection of design problems in IC development methodologies. The availability of SystemVerilog linting aids the adoption of unfamiliar, advanced coding constructs, which is critical as system-on-chip (SoC) designers get up to speed with the new language.
nLint is the industry's first lint tool for SystemVerilog and reinforces the debug leader's overall support for the language as an integral component of its VerdiT and Debussy® Debug Systems. Novas has already completed implementation of SystemVerilog 3.0, SystemVerilog 3.1a Assertions, and can now parse and load the remainder of the SystemVerilog 3.1a standard source code throughout its product line. The Company is also collaborating directly with other industry leaders, the Accellera and IEEE standards organizations, as well as third-party technology partners to validate SystemVerilog language and tool interoperability with its debug solutions throughout the design and verification flow.
"Productivity-enhancing tools such as Novas' debugging environment and linters are an important part of any robust design flow," remarked Accellera chairman Dennis Brophy. "We applaud Novas' continued support to advance adoption of our SystemVerilog hardware description language standard with their consistent commitment to improve design verification for the EDA user community."
nLint is a HDL design rule checker that enables designers to fully analyze SystemVerilog, Verilog and VHDL source code for syntax and semantic errors. Support for SystemVerilog 3.0 design constructs features a comprehensive set of standard and parameterized rules, including checks to assure proper SystemVerilog modeling with specialized procedural statement blocks. Users of the tool can also implement custom rules using Novas' open application programming interface.
nLint operates on the same underlying knowledge database (KDB) used by the Novas debug systems for access to full connectivity information. This allows designers to check all types of data and visualize design rule violations in their Novas debug environment for further tracing and analysis. Complete information about Novas' integrated design rule checking capabilities is available at: http://www.novas.com/Products/nLint
"Linting will become a key technology that enables designers to become more familiar with the SystemVerilog language and effectively leverage new constructs," noted Dave Kelf, vice president of marketing at Novas. "nLint brings SystemVerilog source code checking and debug automation together for the first time. Designers can verify design rule conformance and enforce SystemVerilog coding standards and reuse practices, all the while improving their debug productivity with greater understanding of design behavior."
Availability & Pricing
nLint for SystemVerilog 3.0 is currently available in limited production. The general product release is scheduled for the fourth quarter of 2004. Purchased as an option to the Novas Verdi and Debussy Debug Systems, the nLint list price starts at $5,000 U.S. for a one-year subscription license.
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