CIMdata PLM Industry Summary Online Archive
8 September 2004
Company News
FishTail Expands its Sales and Support Operations around the Globe
FishTail Design Automation, Inc . announced the signing of exclusive distribution agreements with both Saros Technology Ltd. in Europe and Advinno Technologies in Southeast Asia. The new distributors join SC HighTech in Japan in marketing FishTail's FocusT timing closure products. The company also has direct sales and support offices in the United States. The distributors will provide customers with front-line sales and support in their regions.
"Focus is a major addition to our existing product offerings," said Carey Sayer, Managing Director of Saros. "We see Focus' ability to automatically extract false and multi-cycle paths from our customer's designs as a huge step forward in helping our customers meet timing closure on critical designs."
"Our goal is to be the leading design solutions company in South-East Asia," stated Terry Teh, Director of Advinno. "Adding the Focus solution to our offerings is a boon to our existing EDA tool suite. Our customers are designing chips where timing is critical and the Focus solution will help to increase designer productivity and improve the quality of their results."
Saros is a high technology distribution company focusing on the sales, marketing and support of EDA software within Europe. It is headquartered near Oxford, England.
Advinno Technologies Private Limited is a privately held design solutions company incorporated in 2002. Advinno provides EDA software solutions, design services and IP to its customers. Through its extensive experience in Integrated Circuits design and leading edge EDA solutions, the company partners with clients to deliver first-pass success products to market faster. Advinno is headquartered in Singapore and has operations in Southeast Asia.
FishTail's FocusT product solves the problem of poor chip-implementation results because of missing timing exceptions by identifying false and multi-cycle paths early in the design cycle-before virtual prototyping and logic synthesis. Using only the synthesizable description and clock definitions, Focus automatically generates the timing exceptions for the design in standard SDC file format for use by downstream implementation tools.
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