CIMdata PLM Industry Summary Online Archive
9 September 2004
Implementation Investments
Toshiba Adopts Apache's RedHawk-SDL for SoC Power Closure
Apache Design Solutions announced that Toshiba, including its U.S. design sites, has adopted Apache's full-chip dynamic power integrity solution to their SoC power closure flow. After extensive evaluation and accuracy correlation, Toshiba selected RedHawk-SDL for its capability to deliver cell-based, vectorless Dynamic Voltage Drop (DvD) including decoupling capacitance analysis and impact to timing verification.
"Apache offers an accurate and mature dynamic power integrity solution critical for the emerging verification challenges of 90nm designs. RedHawk-SDL provides us with the ability to analyze dynamic supply noise, including package effects prior to tapeout," said Tamotsu Hiwatashi, senior manager of planning department, System LSI Design Department, System LSI Division 1 of Toshiba Semiconductor Company. "By adding RedHawk in our signoff flow, we expect to ensure silicon success while reducing production costs through improved yields."
Apache's flagship RedHawk-SDL is a full-chip Vectorless DynamicT physical power integrity solution that fills the critical missing link for physical power flows in 130nm, 90nm, and 65nm SoC designs. Certified by TSMC's 5.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk-SDL delivers the most accurate power integrity solution on the market. It addresses dynamic power issues such as simultaneous switching outputs (SSO) for core, memory, clock, and I/O, as well as the effects of on-chip inductance, package RLC , and decoupling capacitance.
RedHawk-SDL delivers cell-based capacity with transistor-level accuracy and is the cornerstone of Apache's physical power integrity flow. It can be used early in the design flow when physical implementation decisions are being made, and throughout the entire design process. RedHawk-SDL enables designers to examine the timing impact of dynamic voltage drop on high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, power gating, multiple voltage domains, and multiple threshold transistors.
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