CIMdata PLM Industry Summary Online Archive
13 September 2004
Company News
Silicon Design Systems Forms Technical Advisory Board
Silicon Design Systems, Inc. announced it has established a Technical Advisory Board that will consult and advise the company's executives and engineering management on technology directions for its physical design closure solutions. Initial Board members, who bring a wealth of experience, knowledge and talent from industry and academia, include:
Dr. Eby G. Friedman , Distinguished Professor, Director of the High Performance VLSI/IC Design and Analysis Laboratory, and Director of the Center for Electronic Imaging Systems at the University of Rochester. Author of more than 250 papers and book chapters, several patents, and author or editor of seven books, he also is Regional Editor of the Journal of Circuits, Systems and Computers, and editorial board member of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing, Microelectronics Journal, and Journal of VLSI Signal Processing. He was past Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and is a member of the Circuits and Systems (CAS) Society Board of Governors, and on the technical program committee of several conferences. His interests include high-performance synchronous digital and mixed-signal microelectronic design and analysis applied to high-speed portable processors and low-power wireless communications. Professor Friedman worked a dozen years at Hughes Aircraft Company and currently is a research collaborator, consultant, and technical advisor with numerous IC circuit design and CAD companies, large and small. Professor Friedman is a Senior Fulbright Fellow and an IEEE Fellow.
Dr. Sachin Sapatnekar is the Robert and Marjorie Henle professor in the Department of Electrical and Computer Engineering at the University of Minnesota. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits, primarily centered on physical design, timing and simulation issues, and optimization algorithms. Author/editor of five books and published widely in the area of timing and layout, he has held positions on the editorial board of the IEEE Transactions on VLSI Systems, the IEEE Transactions on CAD, and the IEEE Transactions on Circuits and Systems II. A fellow of the IEEE, he has served as Technical Program and General Chair for the Tau workshop and the International Symposium on Physical Design, and been a Distinguished Visitor for the IEEE Computer Society and a Distinguished Lecturer for the IEEE Circuits and Systems Society. Professor Sapatnekar is a recipient of the NSF Career Award, three best paper awards at DAC and one at ICCD, and the SRC Technical Excellence award.
Dr. Naveed Sherwani , president, CEO and co-founder of Open-Silicon, with more than 19 years of experience in technical engineering and general management. Previously, Dr. Sherwani founded and was general manager of Intel Microelectronics Services, where he led efforts to promote the use of disciplined ASIC methodologies to improve design efficiency and time-to-market. He co-architected the Intel microprocessor design methodology and environment used in various leading microprocessors. Dr. Sherwani is the author of the main textbook on physical design widely used at major universities around the world. In addition, he has authored or co-authored three books and more than 100 articles on various aspects of physical design automation and ASICs.
Udi Kra , Chief Technology Officer of Silicon Design Systems, who joins the TAB as a user expert with more than 20 years of experience in the semiconductor industry. Prior to founding Silicon Value - the predecessor company to Silicon Design Systems - and serving as its CTO, he was a member of Digital Equipment Corporation's Semiconductor Design Center design team in Israel.
Silicon Design Systems recently announced K-RouteT, the industry's first truly concurrent routing technology to solve IC design closure issues magnified by submicron and nanometer technology. Its revolutionary adaptive, fine-grained routing architecture (AFRA) simultaneously uses routing, extraction, analysis and optimization engines to complete tightly constrained designs faster and more predictably. The convergent router automatically recognizes and fixes all potential geometrical, timing and signal integrity violations, allowing for smaller design area and significantly improved performance, power consumption and time to tape-out.
Become a member of the CIMdata PLM Community to receive your daily PLM news and much more.
Tell us what you think of the CIMdata Newsletter. Send your feedback.
CIMdata is committed to your privacy. Your personal information will never be sold or shared outside of CIMdata without your express permission.