CIMdata PLM Industry Summary Online Archive
27 September 2004
Product News
AccelChip Inc. Accelerates Digital Wireless Communication and Signal Processing Design with New Intellectual Property
AccelChip Inc. announced that it has extended its AccelWare® Intellectual Property (IP) libraries to include key building blocks for signal processing and communication applications. This new IP enables the acceleration of algorithms running on standard DSP and embedded processors by 10-100x.
AccelWare is parametric IP that provides a direct path to hardware implementation of complex MATLAB toolbox and built-in functions. The new AccelWare blocks extend the range of the existing AccelChip® DSP Synthesis toolset into various real-time, continuous communications and array signal-processing systems, including space-time adaptive processing, wireless signal processing, software-defined radio, global positioning, radar, and sonar. Acceleration of both standard and embedded DSP processors is becoming a key requirement of these next-generation systems, and AccelChip Inc. is working with leading semiconductor vendors to enhance these types of communications designs.
The combination of AccelWare IP with AccelChip DSP Synthesis provides a high level of reuse and portability, allowing designers to migrate existing designs faster. AccelChip's toolset and IPcan also be used to design entire DSP systems or to develop DSP accelerators. A DSP accelerator is a high-speed FPGA or ASIC that interfaces with a DSP processor bus. It is designed to accelerate portions of the overall algorithm in order to achieve a high-performance system.
"The technology drive toward higher bandwidths, increased resolution, and maximum precision are all combining to cause the processor to reach its natural sequential limitations," said Michael Bohm, CTO and vice president of Engineering, AccelChip. "By creating hardware implementations of key aspects of the algorithms, designers are more likely to meet pre-design performance expectations. Our new AccelWare IP enables the rapid development of accelerators that move key algorithms to hardware to enhance system performance and increase throughput."
In an industry that traditionally offers general-purpose IP where only bit widths can be changed, AccelWare's fully parameterized IP provides multiple micro-architectures, or configurations, that enable the blocks to be tailored for specific market application needs, such as throughput, latency, noise, power, frequency, or area. Additionally, the micro-architectures utilize the company's proprietary resource-mapping technology to achieve high quality of results on targeted FPGA architectures.
AccelWare's DSP-oriented IP corresponds to The MathWorks' communication and signal processing toolboxes. Because AccelWare modules generate MATLAB, they are at a higher level of abstraction than traditional netlist or RTL-based (register-transfer level) IP. This enables a greater degree of architectural exploration and market-specific customization, significantly expanding the range of target applications. The additions to the AccelWare IP include parameterized models for a Viterbi decoder, Galoisfield operators, polyphase decimation filters with programmable coefficients, radix-4 FFTs and IFFTs, and FIR filter serial-distributed arithmetic (SDA) and parallel-distributed arithmetic (PDA)architectures.
Availability
AccelWare IP libraries are available immediately. Current AccelWare customers, on support, will receive the models at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email sales@accelchip.com or visit http://www.accelchip.com/sales.html
AccelChip Inc. develops and markets a MATLAB-based algorithmic synthesis environment and intellectual property that automate the development and implementation of DSP designs.
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