CIMdata PLM Industry Summary Online Archive

27 September 2004

Product News

AccelChip Inc. Enhances Interoperability by Joining the Mentor Graphics OpenDoor Program

AccelChip Inc. has joined the OpenDoor program from Mentor Graphics to enhance interoperability between the two companies' respective products.

The AccelChip® DSP Synthesis tool and AccelWare® Intellectual Property bridge the gap between algorithm development and silicon implementation by generating synthesizable VHDL or Verilog and testbenches from MATLAB algorithms. Designed to fit into current design flows, AccelChip DSP Synthesis now provides an integrated verification and implementation flow with the latest versions of Mentor Graphics® Precision® RTL, Leonardo®Spectrum, and ModelSim® synthesis and simulation tools.

"With today's complex design, companies are looking for superior point solutions that, when combined, form a complete flow. Mentor Graphics provides leading solutions for ASIC and FPGA design," said Tom Feist, vice president of Sales and Marketing, AccelChip. "With their tools now integrated into the AccelChip DSP Synthesis environment, our mutual customers now have a complete DSP design automation solution."

"When EDA vendors work together, the users reap the benefits. The OpenDoor program demonstrates our commitment to serve the designer community via enhanced interoperability in the integrated systems design, hardware/software co-design, NT-based design and multiplatform environments," said Juergen Jaeger, marketing director, Design Creation and Synthesis Division, Mentor Graphics. "Strong partner solutions maximize productivity, expand choices and shorten time to market, all of which become increasingly critical factors for success in complex FPGA design. The combination of AccelChip's DSP front-end with our leading FPGA solutions provides a truly comprehensive design environment."

The AccelChip DSP Synthesis tool takes DSP algorithms written as MATLAB M-files and generates synthesizable RTL and testbenches for implementation in FPGAs, ASICs, and structured ASICs. AccelChip allows the designer to keep the M-file as a single design source and driver for design exploration and verification.

 

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