CIMdata PLM Industry Summary Online Archive
27 September 2004
Product News
AccelChip Inc. Improves Quality of Results and Furthers Integration with Key Industry Partners
AccelChip Inc. announced increased functionality for the company's AccelChip® DSP Synthesis product, plus new support for third-party partners' RTL synthesis and simulation tools.
AccelChip DSP Synthesis accelerates the execution of MATLAB algorithms directly into FPGA sand ASICs by providing automatic implementation and verification flows for DSP algorithms. The tool's latest release, version 2004.5, includes support for new FPGA devices, enhanced flows for ASICs, and improved quality of results (QoR).
"With the 2004.5 enhancements, AccelChip extends our DSP synthesis to more complex designs where a language-based flow is essential for compact and efficient algorithm development," said Michael Bohm, CTO and vice president of Engineering, AccelChip. "With the new release, we are targeting advanced array-based designs, such as those found in image processing, radar, sonar, and real time communication, with new functionality that on specific designs decreases area up to 50% and increases sample rates by 10x over previous releases."
AccelChip DSP Synthesis allows designers to explore multiple micro-architectures and fixed-point representations without ever touching their golden MATLAB source. The tool's enhanced floating- to fixed-point conversion and enhanced scheduler provide the designer much better control over trade-offs between throughput, performance, area, and accuracy.
By reducing the size of HDL arrays and automatically removing unreachable code, users of the new 2004.5 version will see an improvement in the QoR in their target silicon. Users can now also take advantage of the new implicit loop unrolling (ILU) functionality, another example of the leadership role AccelChip is taking in the algorithmic-based market. With ILU, AccelChip extends the common explicit loop unrolling, such as "for loops" that are found in other algorithmic tools, to array operations, where the user can specify all or down to the specific type of array to be unrolled; for example, array add, array subtract, array multiply, and matrix multiply.
The enhanced scheduler optimization allows the user to combine the current stage with a previous stage before the loop, which results in increased sample rate. For example, in designs with ten loops, the sample rate could be increased by as much as 10X.
AccelChip DSP Synthesis is designed to fit into current design flows and bridge the gap between MATLAB and RTL. With this release, it offers an integrated verification and implementation flow with any combination of the following products:
• Aldec RivieraT 2004.08
• Altera Quartus® II 4.1, Stratix IIT, and CycloneT
• Mentor Graphics Precision® RTL 2004a.75, LeonardoSpectrumT 2004a-63, and
• ModelSim® 6.0
• Synopsys Design Compiler® 2004.06 -SP1 Design Compiler FPGA 2004.06-2
• Synplicity Synplify® Pro 7.6.1
• The MathWork's MATLAB 7 and Simulink® 6.0
• Xilinx ISE 6.02.03i and SpartanT-3
"The intuitive MATLAB user interface, its built-in math and graphics functions, and its powerful programming language make MATLAB the most popular, productive, and accurate DSP design environment today," said Jim Tung, MathWorks Fellow at The MathWorks, Inc. "The combination of AccelChip's 2004.5 release and our new MATLAB 7 provides our mutual customers with a direct path to FPGA and ASIC implementations of DSP algorithms."
AccelChip DSP Synthesis now contains 25 new design examples that allow users to quickly learn about the synthesizable MATLAB coding style and become proficient with the tool. Design examples range from basic mathematical operations, matrix operations, and complex numbers to complex examples for general signal processing (filters and transforms) and communications designs (convolution, interleaving, down-conversion, and up-conversion).
Availability
AccelChip DSP Synthesis, version 2004.5, is available immediately. Current AccelChip customers, on support, will receive the new release at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email sales@accelchip.com or visit http://www.accelchip.com/sales.html
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