CIMdata PLM Industry Summary Online Archive
29 September 2004
Implementation Investments
ChipX Selects SynTest's VirtualScan-Scan/ATPG Tool to Reduce Test Costs for Next Generation Large ASICs
ChipX has announced that it has selected SynTest's VirtualScanT, Scan/ATPG tool, to ensure the quality of its new generation of large ASIC designs and cut the cost of ASIC testing, by reducing the scan-test pin-count on load boards.
"We pride ourselves on offering our customers the lowest cost ASIC solutions and getting them to market faster than any other ASIC alternative," said Elie Massabki, Vice President of Marketing at ChipX. "Upgrading our Design for Test (DFT) tools with VirtualScanT from SynTest is an important step towards our on-going effort to consistently upgrade our development and test capabilities with the most effective tools to service our customers."
"At SynTest, we strive to provide our customers with DFT solutions that allow our customers to produce high quality designs, but reduce semiconductor manufacturing test costs," commented Dr. Ravi Apte, VP Strategy and Business Development at SynTest. "We are very happy that we could provide ChipX with a solution that enables them to achieve high fault coverage on their large chips, yet allows them to reduce their test costs. ChipX are using our VirtualScan to combat rising test costs in a unique manner. We are promoting our VirtualScan as a scan/ATPG tool to generate XtremeCompact scan test data that reduces time and cost on the ATE, and many of our customers like ChipX are now reaping the benefits."
Since 1995, when ChipX emerged as a provider of ASIC solutions, in order to mitigate risk, the company decided to use SynTest DFT methodology, to ensure a predictable outcome, eliminate potential design flaws at the last minute, and achieve high fault coverage.
Today, ChipX faces dual challenges of not only having to achieve high fault coverage on structured ASIC designs that are much larger, more complex, and have lots of memory, but also of having to reduce design times and test costs to stay competitive.
To maintain high fault coverage on large designs, a proportionately large number of scan-chains are required, resulting in high pin counts for scan testing and high costs for load boards for testing on Automatic Test Equipment (ATE). For an ASIC solutions provider handling a multitude of chips per year, these costs quickly take on significant proportions.
SynTest's VirtualScan architecture allows ChipX to have a large number of scan flip-flops in their design, arranged in a large number of short scan-chains, but to significantly reduce-by a factor of five or more-the number of external scan chains that need to be connected to the ATE. Thus, the number of pins on the load boards for scan testing can be significantly reduced and consequently also the costs for the load boards.
Furthermore, VirtualScan generates XtremeCompact scan test data that reduces time and cost on the ATE.
ChipX is a manufacturer of high performance Structured ASICs (Application Specific Integrated Circuits). The company's Structured ASIC technology is widely used in high-end consumer electronics, communications, automotive telematics, computing peripherals, industrial control, medical equipment and military/aerospace systems. Headquartered in Santa Clara, CA, ChipX is a privately held corporation, founded in the U.S. in 1989. The company holds two subsidiaries: ChipX (Israel) Ltd., which performs engineering and product development functions, and ChipX UK Ltd., which manages European operations. For more information, visit the ChipX website at http://www.chipx.com
SynTest Technologies, Inc., est. 1990, develops and markets advanced Design-for-Test (DFT) and Design-for-Debug/Diagnosis (DFD) tools throughout the world, to semiconductor companies, system houses and design service providers. The Company's products improve an electronic design's testability and fault coverage and result in reduced defect levels and reduced slippage in Time-to-Market (TTM). They also reduce overall design and test costs, by helping to reduce design iterations as well as the time and reloads on Automatic Test Equipment (ATE). These products include tools for logic BIST, memory BIST, boundary-scan synthesis, DFT testability analysis, VirtualScan synthesis and ATPG with XtremeCompactT test vectors, concurrent fault simulation, silicon debug and diagnosis. The company, headquartered in Sunnyvale, California, has offices in China, Taiwan, Korea and Japan, and distributors in Europe and Asia including Israel. More information is available at http://www.syntest.com
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