CIMdata PLM Industry Summary Online Archive
29 September 2004
Product News
Synopsys' ASIC Strength Flow Ideal for Designers Prototyping With Complex Xilinx Devices
Synopsys, Inc. announced that Synopsys' Design Compiler® FPGA (DC FPGA) now supports Xilinx' Virtex-4T family of domain optimized FPGAs and ISE 6.3i place and route software. DC FPGA is targeted for designers who prototype ASICs using high-end FPGAs.
Large, complex FPGAs such as Virtex-4 require the ASIC-strength synthesis technology in DC FPGA. DC FPGA along with Synopsys' Formality® formal verification solution and ASIC IP support such as Synopsys DesignWare ® IP products, helps ensure that ASIC designers have a proven, fast path to ASIC prototyping using Xilinx Virtex-4 FPGAs.
"ASIC prototyping customers who require a proven ASIC style design methodology using high-end synthesis and formal verification, can now find a Xilinx-preferred solution from Synopsys," said Steve Lass, director of Software Marketing at Xilinx. "This ASIC methodology supports our new Virtex-4 family, which provides the density and system-level features that many customers need today."
"Designers prototyping in high performance FPGAs such as the Xilinx Virtex-4 family depend on the superior timing performance and ASIC flow compatibility that DC FPGA has to offer," said Gal Hasson, Director of Marketing, ASIC and FPGA synthesis at Synopsys. "We have worked closely with Xilinx to ensure our ASIC-strength design flow, including DC FPGA, DesignWare and Formality, provides our mutual customers with the fastest path to their Virtex-4 FPGAs."
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