CIMdata PLM Industry Summary Online Archive
19 October 2004
Product News
Mentor Graphics Pioneers New DFM Technology by Leveraging Calibre Design-to-Silicon Platform
Mentor Graphics Corporation announced additional functionality for the Calibre® design-to silicon platform in the form of Calibre Transition, Measure and Analyze to address critical design for manufacturing (DFM) requirements. Mentor also outlined its long-term roadmap for future Calibre DFM tools, which will allow users to consider and optimize for manufacturing at various stages in the design flow: design, verification and analysis, tapeout and test.
The Calibre design-to-silicon platform is a comprehensive set of tools addressing the complex handoff between design and manufacturing. The cornerstone of the Calibre design-to-silicon platform is a single, hierarchical data processing engine that allows for the essential interaction and data sharing required between all tools in the platform.
"Design for manufacturing is nothing new, but the degree to which nanometer technologies have created additional yield considerations is unprecedented," said Joe Sawicki, vice president and general manager, design-to-silicon division, Mentor Graphics. "Over the last several years, manufacturing for design, primarily resolution enhancement technology, has been the key to ensuring yield. Now, achieving yield is requiring the EDA industry to pioneer new technology, make significant changes to existing tools, and provide a more robust communication link between design and manufacturing."
The Calibre design-to-silicon platform has been extended to include functionality to address a variety of DFM requirements. To assess yield loss due to via failures, the functionality in DFM Transition allows users to identify via transitions by layer and via count, analyze relevant via statistics, determine layout quality and automatically insert vias where needed. To account for and accommodate new foundry DFM rules, the functionality in DFM Measure helps determine to what degree a design adheres to foundry 'recommended' DFM rules, and presents statistics on adherence for the whole chip, by area and by cell. DFM Measure also enables users to visualize layout features by DFM rule priority, histograms and color maps through Calibre RVE (Results Viewing Environment). DFM Analyze combines DFM rule priority and degree of severity with statistical occurrence information by region or cell.
Mentor is currently working with advanced customers on additional DFM capabilities that address areas such as litho verification, a technology that will show designers how the intrinsic fluctuations of the manufacturing process can distort the layout's final image. Another area of on-going development is feature yield analysis, a capability that identifies which features are most inclined to be at risk of failure, assesses the relative impact of the risk, and helps designers use that information to develop more robust design and feature-aware Test methodologies. In addition, Mentor is preparing to introduce the Manufacturing Integration Initiative (MII), in which the Calibre design-to-silicon platform can be leveraged by mask and wafer inspection equipment to guide a more proactive and judicious metrology scheme, based on a sophisticated understanding of the chip layout, and its interaction with the process.
Nanometer technology forces the EDA industry to create technology that allows designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process. Synthesis, place and route, cell design, parasitic extraction, physical verification and wafer test all need to add capabilities that account for as many issues as possible.
Because yield issues accelerate with each new process node, the time required to bring a new process to acceptable yield levels has increased. Before designing and adopting a DFM methodology, it is important to understand the types of yield defects and the impact each has on correction and analysis methods in development at manufacturers. These defect areas include random (typically associated with particle defects), systemic (induced by the process or lithography applications) and parametric (which cause timing or other failures as a result of device physics and interconnect effects). Yield that is limited by defects, although still at issue, has been supplanted by yield limited by features; that is, the failure to form features due to shrinking geometries.
At the 65nm node, it will be even more important to take a holistic approach to DFM, especially in terms of understanding the inherent characteristics in the manufacturing process, and articulating that knowledge in tools, both upstream to design and downstream to test. Like traditional design rule checking (DRC), at 90nm and 65nm, DFM becomes, to a large extent, a full-chip problem: data must be made available in its full context. This means having access to DFM yield-limiting issues in a cross-layer and cross-hierarchical sense. It may be possible to improve the manufacturability of one layer by manipulating another. Similarly, a cell with no known manufacturability issues may significantly impact the manufacturability of a full-chip when placed into context.
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