3 December 2004
Sequence PhysicalStudio Offers Leading S3 Graphics Chip Fastest Available Reduction of Timing and Noise Iterations
Sequence Design announced that S3 Graphics, a leading graphics solutions company, has benefited from the company's PhysicalStudioT optimization software by reducing timing and noise violations on S3 Graphics' leading graphics processors.
PhysicalStudio concurrently analyzes and optimizes chip timing and signal integrity, before routing in an avoidance mode and after detailed routing in a post-route correction mode, thereby ensuring significant reductions in timing and signal integrity violations.
"When we increased the complexity of our graphics processors, we needed a tool that could handle the timing and signal integrity challenges inherent in higher gate-count designs," said Michael Shiuan, vice president of engineering at S3 Graphics. "Building this complex 130 nanometer, high-frequency, 10 Million+ Gate system-on-a-chip required a state-of-the-art push down flow approach for top level optimization. PhysicalStudio is the best chip- and block- level signal integrity analysis and optimization tool we have used-the number of timing and noise violations it eliminates is extraordinary!"
According to XinChang, engineering manager at S3 Graphics, "PhysicalStudio's push-down flow allowed the designer to analyze and optimize timing and signal integrity on the full-chip level and generate ECOs that were pushed down to the individual blocks in the design. This unique capability in PhysicalStudio achieved a turnaround in hours, for full-chip timing and signal-integrity closure, something that takes a week to accomplish with competing tools. The ECOs were seamlessly integrated into S3 Graphics' Cadence place & route flow."
PhysicalStudio enabled designers at S3 Graphics to:
Recover 17% slack (750ps slack on a 225-MHz design)
Fix 1750+ timing violations resulting from crosstalk delay
"A comprehensive power integrity flow is necessary for today's SoC design, beginning at RTL clear through to a tape-out tool like PhysicalStudio that optimizes signal-integrity, power and timing," said Vic Kulkarni, president and CEO, Sequence Design. "We are pleased that S3 Graphics was able to accelerate their design cycle time through the optimization functionality available in PhysicalStudio."
PhysicalStudio is the optimization stage in Sequence's NanoCool power integrity flow. The flow includes RTL power analysis, voltage-drop analysis and optimization, as well as leakage power reduction. Details may be found at: http://www.sequencedesign.com/2_solutions/NC-DataSheet_New.pdf
Sequence recently launched the NanoCool Low-Power Design seminar series with co-sponsors Artisan Components and Sun Microsystems. Additional inquiries on NanoCool seminars may be directed to firstname.lastname@example.org .
PhysicalStudioT is the industry's first design closure tool to predict and correct chip timing, power, and signal integrity issues concurrently, before and after routing. It gives users the ability to interactively optimize hierarchical, multi-million gate SoC designs at the block-level as well as at top-level. PhysicalStudio integrates into popular Cadence, Synopsys and Magma third-party routing tools to enable existing physical flows to reach fast, predictable design closure in silicon geometries below 180 nanometers (nm).
Post-route correction closes timing faster and at higher clock speeds than other methods
Repairs cross-talk delay, glitch, IR drop, and electro-migration failures
Analyzes and optimizes timing and signal integrity concurrently
Supports both block-level and top-level optimization
Large 10M+ gate SoC designs optimized hierarchically
Works with existing physical design infrastructure
Enables design flows to achieve design closure at 180 nm and below
S3 Graphics Co., Ltd., a VIA Technologies joint venture company, is a leading supplier in the 3D enabled PC graphics market. S3 Graphics ships low power, high performance, commercial grade 3D graphics sub-systems to top tier notebook manufacturers.
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