CIMdata PLM Industry Summary Online Archive
14 December 2004
Product News
Agilent Technologies and Synopsys Announce Industry-First Scan Diagnostics Reference Methodology
Agilent Technologies Inc. and Synopsys Inc . announced an industry-first scan diagnostics reference methodology. The solution speeds fault localization and failure analysis for semiconductor design and test engineers faced with identifying device failures under increased time-to-market pressure.
A result of the companies' three-year strategic alliance, the methodology is enabled by the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAX® automatic test pattern generation (ATPG) solution, in conjunction with the Agilent 93000 SOC Series test platform. This combination of tools automates the bidirectional information sharing between electronic design automation (EDA) and automatic test equipment (ATE) required for scan diagnostics.
As process geometries shrink and device complexity grows, identifying device failures becomes increasingly difficult. The demand for shorter time to market and lower product cost makes rapid diagnostics and fault localization vital during the first silicon evaluation and production ramp up. EDA companies have begun to offer fault localization tools, but they require failure information from automatic test equipment. Until now, a standardized and supported means for sharing information from ATE has not been available.
"Our customers want us to link design and test more closely in order to lower the overall cost of test," said Tom Newsom, vice president and general manager of Agilent's SOC Business Unit. "Our strategic alliance with Synopsys has successfully contributed toward bridging the gap between EDA and ATE."
"Automating failure and yield diagnostics is a critical business issue for our customers," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Synopsys' collaboration with Agilent is key to improving manufacturing test flows, and together we are demonstrating further leadership by delivering a diagnostics reference methodology."
The Agilent 93000 SmarTest PG 2.2 offers a transition from the EDA environment to the industry-leading capabilities of the Agilent 93000 SOC Series, which speeds test development for functional and scan tests. SmarTest PG 2.2 provides a scan failure map for viewing scan failures on the Agilent 93000 SOC Series in their native scan context, speeding first silicon debug. It features a simplified user interface and command-line operation, and supports industry-standard EDA input formats, including Standard Test Interface Language (STIL), Waveform Generation Language (WGL), Value Change Dump (VCD), Extended VCD (EVCD) and Core Test Language (CTL).
Further information about the Agilent 93000 SmarTest PG 2.2 is available at http://www.agilent.com/see/smartestpg . Information about Agilent's semiconductor test products is available at http://www.agilent.com/see/atenews .
The Agilent 93000 SOC Series is the industry's fastest-growing, lowest-cost scalable platform architecture with more than 900 installed systems worldwide. The Agilent 93000 SOC Series is designed to meet both the demanding performance and cost challenges of SOC testing. Models are configured to span the widest range of applications that may require ultra-high-speed digital data rates, up to 10 Gb/s, and the broadest range of mixed-signal and RF capabilities. With this range of capabilities, the 93000 SOC Series is the first choice for subcontract manufacturers and the preference for high-volume manufacturing. More information is available at http://www.agilent.com/see/soctest .
U.S. Pricing and Availability
The Agilent 93000 SmarTest PG 2.2 is available now for purchase with licensing options ranging from $5,000 to $72,000.
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