CIMdata PLM Industry Summary Online Archive
7 March 2005
Product News
Stelar Tools HDL Explorer Adds Automatic Signal Routing, Automatic Block Movement and Connection, and Full VHDL Support to Dramatically Reduce RTL Closure Time
Stelar ToolsT, Inc., a venture-backed provider of EDA tools, announced a new and significantly enhanced release of its flagship product, HDL ExplorerT. HDL Explorer is the first EDA tool to deliver rapid RTL Closure, the process of getting a design clean at the register-transfer level, before synthesis, which results in a more than 30 percent reduction in the time it takes to get a complex ASIC, SoC, structured ASIC, or FPGA design from concept through synthesis. HDL Explorer provides a unique combination of technology for creating new designs and for exploring new and legacy designs and testbenches-all while using best known methods (BKMs). To enhance design reuse, HDL Explorer lets designers automatically route signals, move blocks, and connect signals through the hierarchy. In addition, it provides the ability to encapsulate random logic into a new block or break an existing block into smaller blocks. And the tool now features full Verilog, VHDL and mixed Verilog/VHDL support. All the new enhancements further accelerate RTL Closure.
According to Stelar's vice-president of marketing, Steve Sapiro, "Our customers spend a great deal of time manually routing signals and moving and reconnecting modules in a design hierarchy. HDL Explorer now automates these manual tasks, making it a must-have tool for anyone doing HDL design."
Stelar Products Now Available Through Distributors in Europe and India
According to recently appointed sales manager Ben Franklin, "I am excited about being able to offer Stelar Tools HDL Explorer to our European distribution network and European prospects. HDL Explorer has features that customers require to keep their design times short and reduce their time-to-volume production. Several large European electronics companies are very interested at this time, and we anticipate some major deployment announcements in the near-term. We anticipate great interest at our stand at D.A.T.E. this week with the latest HDL Explorer announcement."
The New Release of HDL Explorer:
Automatically Routes Signals Through the Hierarchy -HDL Explorer is the first tool to let designers automatically route signals from one point to another in the design hierarchy, eliminating manual signal routing. This saves valuable time and greatly reduces the introduction of errors-netting a significant reduction in the number of times a design must be redone.
Automatically Moves and Reconnects Design Blocks -Designers often need to move design modules or break single modules into multiple modules within their design hierarchy. This used to mean they had to manually remove wires, break up modules, move modules or encapsulate multiple modules into a single module, and create the ports, pins, and wires on each module. HDL Explorer is the first EDA tool that automates this process. A designer simply selects a module or a group of modules and drags the selection to the new location. Depending on the designer's intent, HDL Explorer automatically encapsulates the group of modules into a mega module, or just selects the single module, and then connects the new wires. This greatly accelerates design time and eliminates manual intervention, thereby reducing errors.
Supports VHDL, Verilog, and Mixed Verilog/VHDL Designs -HDL Explorer now addresses a much broader range of designs with its support for Verilog, VHDL, and mixed Verilog and VHDL designs.
HDL Explorer Speeds RTL Closure for New and Legacy Designs
HDL Explorer can benefit designs of every size, with maximum benefit for designs of two million gates or more. Using five patent-pending technologies, HDL Explorer lets users create new design entities, IP, connections and testbenches, and stitch blocks together. It also lets them explore and analyze existing designs and testbenches using various views, helping users quickly find and fix design errors and define and manage the design-verification interface. HDL Explorer gives design managers the ability to better manage design projects with easy-to-extract status and statistical information from a large design. With these features, HDL Explorer facilitates rapid RTL Closure to provide a huge time savings over traditional approaches.
Pricing and Availability
The new release of HDL Explorer will be available worldwide on Linux and Windows XP platforms in Q2 2005. It may be purchased through Stelar distributors on a per-seat or project basis. Pricing starts at $7,900 (U.S.) for an annual single-user time-based license. Contact Stelar Tools in the U.S. at +1-503-539-7436, in Europe at +49-89-907-75215, or at sales@stelartools.com.
Further information about Stelar can be found at http://www.stelartools.com .
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