CIMdata PLM Industry Summary Online Archive
22 March 2005
Product News
Renesas Technology Integrates Mentor Graphics 0-In Assertion Synthesis for Assertion Based Verification Flow
Mentor Graphics Corporation announced that Renesas Technology Corp. completed a joint development effort that integrates the Mentor Graphics® 0-In® Assertion Synthesis technology and assertion-based verification flows with Renesas' LogicBench rapid prototyping system. The cooperation results in a solution that gives Renesas the ability to specify assertions in any format and have them used throughout the verification process, from C-based system design through FPGA prototyping. Assertions provide the ability to detect and diagnose bugs earlier and faster than traditional methods enabling design teams to reach verification closure more effectively and efficiently.
Renesas specifically developed their LogicBench prototyping system to begin hardware-software integration and debugging well before silicon is available. However, use of FPGA-based prototyping methods can limit the ability to locally detect and debug hardware design errors. To address this problem, Renesas required technology that enabled assertions that are specified in any format, including standard assertion languages and libraries, to be compiled directly into LogicBench, providing observability comparable to software simulation. As the industry's leading solution for assertion-based verification, the 0-In Assertion Synthesis tool was chosen and extended to support the Renesas' verification flow.
"We needed an assertion-based verification method that includes simulation and formal verification to strengthen our verification solution based on LogicBench," stated Mr. Osamu Tada, department manager of System Level Design and Verification Technology, Design Technology Division, LSI Product Technology Unit of Renesas Technology Corp. "We selected Mentor's 0-In Assertion Synthesis technology because it provides the best solution for our target."
Assertion-based verification provides the observability and controllability required to verify today's complex system-on-chip (SoC) designs. Applying the 0-In Assertion Synthesis tool simplifies the specification of assertions by automatically extracting design data (for example: clocks, resets and variable names) from register-transfer level (RTL) code. This design inference capability allows assertions to automatically adapt to design changes and significantly reduces the maintenance required as the design evolves. Compared to other methods, the 0-In Assertion Synthesis technology significantly simplifies the task of finding and determining the cause of bugs. The 0-In Assertion Synthesis supports all standard assertion formats including Accellera's Property Specification Language (PSL), SystemVerilog assertions (SVA), the Open Verification Library (OVL), the CheckerWare® tool, and the 0-In assertion library. The assertions generated by the 0-In Assertion Synthesis system can be used with standard simulators, formal engines, emulators or hardware prototyping systems.
"Leading design teams require a full-range of assertion checkers and protocol monitors that are interoperable with leading verification tools. In order to take full advantage of the capabilities on LogicBench, Renesas needed a unique capability for gathering and reporting error detection and coverage information," stated Steven D. White, general manager of Mentor Graphics 0-In Verification Business Unit. "Our assertion synthesis technology provided the right answer."
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