CIMdata PLM Industry Summary Online Archive
28 March 2005
Company News
42nd Design Automation Conference Announces Strong Technical and Business Program
The Design Automation Conference (DAC) announced a strong technical program and a full complement of business-related sessions to meet the varied interests and requirements of the 10,500 plus attendees of this annual conference, scheduled for June 13 to 17, 2005 in Anaheim, Calif.
This year DAC has added "Wireless Wednesday" to the program to offer attendees and exhibitors an opportunity to participate in a series of technical sessions, DAC pavilion events and special activities on the exhibit floor highlighting wireless design.
"This year DAC's program committee reviewed more than 730 paper submissions to arrive at this stellar program," said Bill Joyner, general chair of the 42nd DAC. "As always, the DAC program will deliver an array of timely technical and business information to all of our attendees, from designers to executives."
The 42nd DAC's technical program features technical sessions on all aspects of chip design including low power design, design-for-manufacturing (DFM), embedded hardware and applications, interconnect and signal integrity, verification, simulation, reconfigurable devices and high-level synthesis. A total of 13 tutorials, four workshops, 18 DAC Pavilion presentations and 57 technical sessions make up the more than 200 technical presentations that will take place at the conference.
This year's program features one full-day tutorial on Monday, June 13, on design-for-manufacturing at 65nm and below. Five full-day tutorials will be offered on Friday, June 17 on C-based design, functional hardware verification, advancements in energy-efficient design, statistical performance analysis and optimization of digital circuits, and design of SoCs with embedded processors.
A series of seven vendor-presented, hands-on tutorials will be offered throughout the week focusing on core-based SOC design and RTL handoff.
Building on the success of the Business Day at the 41st DAC, this year a special Management Day has been added to the program. On Tuesday, June 14, a series of business and technology topics will be discussed to offer mid- and senior level managers information on choosing flows and methodologies for SoC design and which emerging solutions are necessary. In addition, registration in the Management Day includes the EDA Business Forum Luncheon and Management Day cocktail party to give attendees the opportunity to network with their peers in the industry.
This year DAC will continue to offer a full schedule of panels and presentations in the DAC Pavilion on the Exhibitor Floor, which are open to all attendees. There will be a "Hot" products at the 42nd DAC presentation. Other topics of the lively technical and business discussions include verification methodology, ESL, DFM and Wireless.
The attached addendum provides more detail on conference highlights.
Registration
To register for DAC visit http://www.dac.com or call 800-321-4573 in the U.S. to request registration materials. The advance conference registration discount deadline is May 16th.
DAC is the annual event where the electronics design community meets for a week-long forum of information exchange on management practices, products, methodologies and processes. Attended by more than 10,500 developers, designers, researchers, managers and engineers from leading electronics companies and universities worldwide, it offers a technical program covering the industry's hottest trends. Its vibrant exhibit floor includes more than 225 companies, many of whom are startups just introducing their first products. The conference is sponsored by the Association for Computing Machinery's Special Interest Group on Design Automation (ACM/SIGDA), the Circuits and Systems Society and Computer Aided Network Design Technical Committee of the Institute of Electrical and Electronics Engineers (IEEE/CASS/CANDE) and the Electronic Design Automation Consortium (EDA Consortium). More details about DAC are found at: http://www.dac.com .
Addendum: 42nd DAC Highlights
Keynote Speakers
On Tuesday, June 14, Dr. Bernard "Bernie" Meyerson will present the opening keynote address titled, "How Does One Define 'Technology' Now That Classical Scaling Is Dead (and Has Been for Years)?" He will discuss the demise of the classical scaling of semiconductor technology and the emergence of new strategies to drive continued progress in IT performance, such as Holistic Design. On Thursday, June 16, Dr. Ron Rohrer will deliver "Innovation in the EDA Business Need Not Be an Oxymoron," in which he will outline a renewable model for fostering EDA innovation as a managed process.
Best Wireless Papers from ISSCC
As part of this year's new Wireless Wednesday, the annual special session highlighting the best of ISSCC papers will present the following ISSCC papers focused on leading technology topics in wireless design: "A 135Mb/s DVB-S2 Compliant CODEC Based on 64,800b LDPC and BCH Codes;" "A 180Ms/s 162Mb/s Wideband Three-Channel Baseband and MAC Processor for 802.11a/b/g;" "A 1V 433MHz/868MHz 25kb/s FSK 2kb/s OOK RF transceiver SoC in Standard Digital 0.18um CMOS" and "A 24GHz Phased-Array Transmitter in 0.18um CMOS."
Special Sessions
The following nine special sessions in the technical program will feature presentations by leading scholars and engineers on the following topics:
Tuesday June 14:
10:30-12:00-Error Tolerant Design
Wednesday June 15:
8:30-10:00-Closing the Power Gap between ASIC and Custom
10:30-12:00-The Titanic:" What Went Wrong?
14:00-16:00-Emerging Directions in Wireless
16:30-18:30-Best of Wireless at ISSCC
Thursday June 16:
8:30-10:00-MATLAB-the Other Emerging System Design Language
10:30-12:00-Formally Verifying Your 10-Million Gate Design
14:00-16:00-DFM and Variability
16:30-18:00-Hierarchical Design and Design Space Exploration of Analog ICs
DAC Panel Sessions
This year's eight technical program panel discussions will offer attendees the chance to listen to, and participate in lively debates on the following topics:
• Is Methodology the Highway Out of Verification Hell?
• My Giga Hertz, Does Yours?
• Modern Design: Perfection or Nothing
• Wireless Platforms: GOPS for Cents and MilliWatts
• Platform ASIC Apprentices: Who Will Survive Your Boardroom
• Should Our Power Approach be Current?
• ESL: Tales from the Trenches
• DFM Rules!
DAC Pavilion (Exhibit Floor Booth 2269)
18 presentations have been scheduled for the DAC Pavilion. Throughout the four days of the exhibition there will be a mix of panels, featured speakers, award presentations and other discussions. Scheduled presentations include:
• A Conversation with the Marie R. Pistilli Women in EDA Achievement Award
• Dataquest at DAC with Gary Smith: EDA Trends and What's Hot at DAC?
• EDA: Why Invest?
• Software Piracy: Can the EDA Industry Survive it?
• The Real Cost of Linux
• Ask the CTO: Everything You Wanted to Know, but Were Afraid to Ask
• Is There No Way Out for IP Vendors?
• Student Design Contest Award Presentations
• Wireless Design: Can You Hear Me Now?
• Did Assertions Help You C.Y.A. on Your Last Design?
• The Business of Standards
• IP Interoperability-Making the Pieces Fit
• DFM-A Reality Check
• Verification Success: Users' Secret Sauce
• ESL: Is it Just MATLAB and Excel Spreadsheets?
• EDA Serial Acquirees: You Can Run But You Can't Hide
• Perspectives on Wireless I: Gadi Singer Sings
• Perspectives on Wireless II: Mike Muller-The Wireless Carnac the Magnificent
Best Paper Awards
As many as five best paper awards in the amount of $1,000 each will be announced at the keynote on Thursday, June 16.
Workshops
The following special interest workshops will be offered this year:
• UML for SoC Design
• Integrated Design Workshop
• Workshop for Women in DAC
• Introduction to Chips and EDA for a Non-Technical Audience
Full-Day Tutorials
This year's full-day tutorial line-up will offer design engineers valuable, in-depth technical training covering the following key design areas:
On Monday, June 13:
• Design for Manufacturing at 65nm and Below
On Friday, June 17:
• System-level and Reconfigurable DesignVerification
• Testing and Silicon Debug
• Implementation (performance analysis, DFM)
• Design of SoCs with Embedded Processors
Hands-on Tutorials
The following tutorials will be offered on RTL Handoff:
On Monday, June 13:
9:00-12:00
TeraSystems RTL Handoff Technology
TeraSystems Inc., LSI Logic Corp., NEC Electronics Corp, Kawasaki Microelectronics
14:00-16:00
Enabling RTL Handoff via Predictive Development
Atrenta Inc., Conexant Systems, Inc.
The following tutorials will be offered on Core-Based SoC Design: On Tuesday, June 14:
14:00-17:00
Designing Extendable Cores with Low-Cost Metal Programmable Technology
Magma Design Automation, Inc., CoWare, Inc., MIPS Technologies, Inc., Virage Logic Corp.
On Wednesday, June 15:
9:00-12:00
Design of Multi-Core Systems with SystemC and Retargetable Processor Tools
Target Compiler Technologies, Mentor Graphics Corp.
14:00-17:00 Using Configurable Processors to Replace RTL Blocks
Tensilica, Inc., Virage Logic Corp.
On Thursday, June 16:
9:00-12:00
Virtual System Prototypes for Core-Based SOC Design
VaST Systems Technology, StarCore, LLC
14:00-17:00 Core-Based SOC Design
IBM Corp., Cadence Design Systems, Inc., Synopsys, Inc.
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