CIMdata PLM Industry Summary Online Archive
4 April 2005
Implementation Investments
Atmel Adopts Synopsys' VCS Native Testbench and Systemverilog Assertions
Synopsys, Inc. announced that Atmel Corporation, a global supplier in the development and fabrication of advanced semiconductor solutions, has adopted the latest release of Synopsys' VCS® comprehensive RTL verification solution for verification of its devices. Atmel development teams are taking full advantage of the built-in verification features of the VCS solution, including Native Testbench (NTB) technology, SystemVerilog assertions, and built-in coverage. By natively integrating a comprehensive set of bug-finding technologies, the VCS solution offers up to 5x faster verification performance compared with using stand-alone tools. The VCS solution is a key component of the Synopsys DiscoveryT Verification Platform.
"VCS' NTB has been easy to adopt and has proven itself by providing increased productivity in validating our designs," said Eric Costello, design methodology manager at Atmel. "The availability of native verification technologies in a single tool allows us to easily deploy advanced verification techniques. In one recent project, we found benefit by relying on NTB's constraint solver to create complex test sequences versus the traditional approach of writing directed tests. Using the tool to exercise the part saved us time and resources, found bugs and let us run more cycles."
Atmel also takes advantage of the VCS solution's built-in support for SystemVerilog assertions, functional coverage and code coverage as part of a coverage-driven verification methodology. SystemVerilog assertions are written by designers to capture elements of the verification plan, enabling progress to be tracked over time and increasing confidence in verification schedules. The combination of the VCS solution's native assertion, testbench and comprehensive code coverage engines provides an effective mechanism for tracking verification progress and effectiveness.
"We make extensive use of the VCS solution's built-in coverage features to help monitor progress to our verification plan," continued Eric Costello. "SystemVerilog assertions in particular have quickly become an important part of our verification and debug strategies, and are being eagerly adopted by our design teams."
"The wealth of bug-finding technologies in the VCS solution make it a truly comprehensive RTL verification solution," said Farhad Hayat, vice president of Marketing, Verification Group, Synopsys, Inc. "With full-featured testbench capabilities, built-in assertions and a wide range of coverage metrics, customers such as Atmel are achieving much better verification results with less effort in less time."
The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, DesignWare® verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemCT and OpenVera® and Synopsys' proven Reference Verification Methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.
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