CIMdata PLM Industry Summary Online Archive
13 April 2005
Product News
Synopsys to Distribute Tower Semiconductor's 0.18- and 0.13-Micron Silicon Libraries within DesignWare Library
Synopsys, Inc. and Tower Semiconductor Ltd., a pure-play independent specialty foundry, announced that Tower's in-house set of 0.18-micron standard cells, I/Os and memory libraries are now available through Synopsys' DesignWare® Library. As a result, more than 25,000 DesignWare Library licensees now have access to Tower Semiconductor's 0.18-micron libraries, at no additional charge, for use in complex system-on-chip (SoC) designs. Starting in the third quarter of this year, licensees are expected to have access to Tower's 0.13-micron libraries.
The 0.18-micron libraries include a complete set of views fully validated in silicon in high-volume production, as well as views for third-party EDA tools. The library distribution agreement with Synopsys also includes the future distribution of Tower's 0.13-micron libraries through the DesignWare Library.
"We have successfully used the Tower 0.18-micron standard cells and I/Os in our design. The high quality of the library and the expert support staff from Synopsys enabled us to smoothly meet our design goals," said Alan Tsun, vice president of ESP development engineering at QuickLogic. "Including the Tower library in the DesignWare Library means our designers will have easy library access with effective support and regular updates. This greatly simplifies our IP procurement and administrative processes."
"Distributing our technology-optimized libraries through the Synopsys DesignWare Library enables us to reach out to a very large number of SoC designers who are targeting our 0.18-micron technologies," said Rafi Nave, vice president of customer services at Tower Semiconductor. "We worked closely with Synopsys to ensure a smooth path to silicon and the support given by Synopsys' experts will help ensure our customers' design success."
"With this library distribution agreement, Synopsys and Tower are answering designers' requests for a complete RTL-to-GDSII design environment with streamlined access to essential IP," said Guri Stark, vice president of Marketing, Synopsys Solutions Group. "The addition of Tower's foundry libraries to the DesignWare Library IP portfolio provides our mutual customers with an even greater array of choices when they need reliable, proven IP."
Pricing and Availability
The Tower 0.18-micron standard cells, I/Os and memories are currently available for no additional cost to all current DesignWare Library licensees. Tower's 0.13-micron simulated libraries are expected to be available in the third quarter of this year. Requests to download the Tower libraries can be made at http://www.synopsys.com/dwrequest.
Synopsys DesignWare IP enables designers to create and verify complex SoCs, ASICs and FPGAs. The broad IP portfolio includes synthesizable implementation IP, hardened PHYs and verification IP. DesignWare IP, combined with Synopsys' IP development methodology, extensive investment in quality and comprehensive worldwide technical support, gives designers a faster, more predictable and lower risk path to chip success. The DesignWare Library portfolio includes foundry libraries, verification IP, AMBAT bus IP and peripherals, memories, building block IP and microcontrollers. All are available under one license with no additional costs, per use fees, or royalties. For a complete directory of Synopsys IP visit: http://www.synopsys.com/ipdirectory .
Tower Semiconductor Ltd. is a pure-play independent specialty foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13-microns; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. The Tower Web site is located at http://www.towersemi.com .
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