CIMdata PLM Industry Summary Online Archive
25 April 2005
Product News
Cadence PCI Express Solution Passes PCI-SIG Compliance Testing; Tested, Integrated IP Reduces Risk, Shortens Time to Market for PCI Express Designers
Cadence Design Systems, Inc. announced that its PEX Endpoint Controller IP, integrated with Rambus' PCI Express(1) PHY IP, has passed PCI-SIG(1) compliance testing and been added to the PCI-SIG Integrators List.
Cadence® has taken a vertical approach to meeting the needs of PCI Express customers, combining technologies from industry leaders to enable customers to reduce risk and increase productivity. In addition to design and verification IP, the vertical approach combines emulation, board design and protocol analysis tools targeted at the PCI Express architecture. In preparing for the Compliance Workshop, where devices need to pass compliance and interoperability testing, verification IP from Denali and PCI Express analyzers from Catalyst helped Cadence develop a higher-quality product.
Chuck Trefts of Catalyst, a veteran of many PCI-SIG Compliance Workshops, said, "The performance of the Cadence/Rambus test board against our PCI Express compliance test suite was excellent, among the best PCI Express solutions I have seen."
"The PCI-SIG is pleased to see Cadence's support for the PCI Express architecture," said Al Yanes, PCI-SIG president. "Cadence's addition to the Integrators List underlines the value of our approach to empower member companies and shorten the design cycle of innovative products based on the PCI Express technology."
Passing compliance testing is a significant milestone for the serial link portfolio agreement announced in July 2004 between Cadence and Rambus. In March, Cadence and Rambus announced that Open-Silicon, a fabless ASIC company, licensed multiple Rambus RaSerT serial link offerings through the Cadence-Rambus reseller program.
The PCI Express technology has become established as the leading high-speed serial interconnect. However, its complex digital protocol layers and multi-GigaHertz analog interfaces make design and verification more complex.
"Working with Cadence, we are able to offer high-speed I/O, an unmatched portfolio of off-the-shelf IP backed up with integration and customization services," said Jean-Marc Patenaude, director of marketing, Rambus. "Success in testing at the Compliance Workshop is further evidence of our ability to provide complete, proven interface solutions."
Dirk Wieberneit, vice president and general manager of Product Development Consumer of Micronas, which successfully passed PCI-SIG compliance with its nGene® product line, commented: "The familiarity of Cadence Engineering Service's teams with both PCI Express technology and verification tools from vertical solution members Denali and Catalyst, as well as the excellent cooperation between Cadence and Micronas in verifying the Cadence IP under real application conditions, including the software, were the key success factors in reaching compliance and interoperability." Micronas' nGene® is the world's first dual-channel multimedia controller integrating PCI Express for the PC-TV market.
The PCI-SIG is the special interest group responsible for PCI Express architecture; it owns and manages PCI specifications as open industry standards. The organization defines and implements new industry standard I/O (input/output) specifications as the industry's I/O needs evolve. Currently, more than 900 industry-leading companies worldwide are active PCI-SIG members. For more information about the PCI-SIG visit http://www.pcisig.com .
Under the Cadence-Rambus agreement, Rambus acquired Cadence's serial interface PHYs to add to its serial interface product line. Cadence Engineering Services is able to deliver to its customers tailored design solutions incorporating any of the Rambus serial interface PHYs. Rambus, along with Denali, are members of the Cadence OpenChoice IP Partner program which delivers world-class IP solutions targeted at communications, computer and consumer applications.
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