CIMdata PLM Industry Summary Online Archive
2 May 2005
Product News
New Cadence Incisive Formal Verifier Extends the Power of Formal Analysis to Designers' Desktops; Designers Benefit from Improved Productivity and Increased Quality of Functional Verification
Cadence Design Systems, Inc. announced the release of the IncisiveT Formal Verifier, extending the power of formal analysis to designers' desktops. Combined with Cadence simulation, acceleration and emulation technologies, the Incisive Formal Verifier enables designers to improve the productivity and quality of functional verification earlier in the design and verification process. Customers can reduce production schedules significantly because design engineers can begin verification as they are designing the chip.
An integral part of the Incisive verification platform's assertion-based verification (ABV) offering, formal analysis does not require a set of test vectors, which means functional bugs can be detected months before testbench development and simulation. Incorporating Formal Verifier into verification flows can help minimize silicon re-spins and improve the quality of design. Formal analysis methods can statically expose corner-case functional bugs that are difficult-sometimes impossible-to detect with dynamic verification techniques like simulation, acceleration or emulation.
"We conducted an extensive evaluation of leading static property checkers and chose the Incisive Formal Verifier for production flow adoption," said Bernd Zombek, project manager, Siemens. "It enables us to begin verification months before the testbench is ready, which improves productivity for our design and verification teams. Incisive Formal Verifier is easy to adopt and almost anyone can use it after some basic assertion training."
Incisive Formal Verifier employs the same set of assertions supported across the entire Incisive platform. With this broad support, designers can begin writing and verifying assertions using formal analysis prior to simulation. As the blocks are integrated, the same assertions can be used in the Incisive Unified Simulator and later in the Incisive Palladium II accelerator/emulator, enabling a continuous, synergistic flow throughout the entire platform. While Formal Verifier works synergistically with Incisive Unified Simulator, it can also be deployed in flows that use other simulators.
Incisive Formal Verifier supports designs using Verilog, SystemVerilog, VHDL and mixed-language environments, with assertions written in PSL and SVA, or using OVL and the Incisive Assertion Library. A wide range of complementary leading-edge formal engines is provided, along with automatic assertion extraction, formal coverage metrics, and advanced usability and debug features.
"The introduction of the Incisive Formal Verifier product represents an evolutionary change in how designers will design and verify large, complex chips," said Mitch Weaver, vice president and general manager, Systems and Functional Verification, Cadence. "Functional verification has been a significant challenge in the chip-design process and having the ability to formally verify assertions substantially increases our customers' productivity, while improving the quality of the design."
The Incisive Formal Verifier has already been deployed by several key customers and is currently available to the general public. For more information, please visit: www.cadence.com/company/newsroom/press_kits/index.aspx .
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